669 lines
15 KiB
C++
669 lines
15 KiB
C++
#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <string.h>
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#include <errno.h>
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#include <signal.h>
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#include <ctype.h>
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#include <termios.h>
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#include <sys/types.h>
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#include <sys/mman.h>
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#include <sys/stat.h>
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#include "fpga_io.h"
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#include "file_io.h"
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#include "input.h"
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#include "osd.h"
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#include "fpga_base_addr_ac5.h"
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#include "fpga_manager.h"
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#include "fpga_system_manager.h"
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#include "fpga_reset_manager.h"
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#include "fpga_nic301.h"
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#define FPGA_REG_BASE 0xFF000000
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#define FPGA_REG_SIZE 0x01000000
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#define MAP_ADDR(x) (volatile uint32_t*)(&map_base[(((uint32_t)(x)) & 0xFFFFFF)>>2])
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#define IS_REG(x) (((((uint32_t)(x))-1)>=(FPGA_REG_BASE - 1)) && ((((uint32_t)(x))-1)<(FPGA_REG_BASE + FPGA_REG_SIZE - 1)))
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#define fatal(x) munmap((void*)map_base, FPGA_REG_SIZE); close(fd); exit(x)
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static struct socfpga_reset_manager *reset_regs = (socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
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static struct socfpga_fpga_manager *fpgamgr_regs = (socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
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static struct socfpga_system_manager *sysmgr_regs = (socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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static struct nic301_registers *nic301_regs = (nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
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static uint32_t *map_base;
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static int fd;
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static __inline void writel(uint32_t val, const void* reg)
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{
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/*
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if(!IS_REG(reg))
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{
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printf("ERROR: Trying to write undefined address: %p\n.", reg);
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fatal(-1);
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}
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*/
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*MAP_ADDR(reg) = val;
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}
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static __inline uint32_t readl(const void* reg)
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{
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/*
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if (!IS_REG(reg))
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{
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printf("ERROR: Trying to read undefined address: %p\n.", reg);
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fatal(-1);
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}
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*/
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return *MAP_ADDR(reg);
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}
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#define clrsetbits_le32(addr, clear, set) writel((readl(addr) & ~(clear)) | (set), addr)
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#define setbits_le32(addr, set) writel( readl(addr) | (set), addr)
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#define clrbits_le32(addr, clear) writel( readl(addr) & ~(clear), addr)
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/* Timeout count */
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#define FPGA_TIMEOUT_CNT 0x1000000
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/* Set CD ratio */
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static void fpgamgr_set_cd_ratio(unsigned long ratio)
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{
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clrsetbits_le32(&fpgamgr_regs->ctrl,
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0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
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(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
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}
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static int fpgamgr_dclkcnt_set(unsigned long cnt)
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{
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unsigned long i;
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/* Clear any existing done status */
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if (readl(&fpgamgr_regs->dclkstat))
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writel(0x1, &fpgamgr_regs->dclkstat);
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/* Write the dclkcnt */
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writel(cnt, &fpgamgr_regs->dclkcnt);
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/* Wait till the dclkcnt done */
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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if (!readl(&fpgamgr_regs->dclkstat))
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continue;
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writel(0x1, &fpgamgr_regs->dclkstat);
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return 0;
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}
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return -ETIMEDOUT;
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}
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/* Check whether FPGA Init_Done signal is high */
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static int is_fpgamgr_initdone_high(void)
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{
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unsigned long val;
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val = readl(&fpgamgr_regs->gpio_ext_porta);
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return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
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}
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/* Get the FPGA mode */
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static int fpgamgr_get_mode(void)
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{
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unsigned long val;
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val = readl(&fpgamgr_regs->stat);
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return val & FPGAMGRREGS_STAT_MODE_MASK;
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}
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/* Check whether FPGA is ready to be accessed */
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static int fpgamgr_test_fpga_ready(void)
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{
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/* Check for init done signal */
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if (!is_fpgamgr_initdone_high())
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return 0;
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/* Check again to avoid false glitches */
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if (!is_fpgamgr_initdone_high())
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return 0;
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
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return 0;
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return 1;
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}
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/*
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// Poll until FPGA is ready to be accessed or timeout occurred
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static int fpgamgr_poll_fpga_ready(void)
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{
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unsigned long i;
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// If FPGA is blank, wait till WD invoke warm reset
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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// check for init done signal
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if (!is_fpgamgr_initdone_high())
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continue;
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// check again to avoid false glitches
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if (!is_fpgamgr_initdone_high())
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continue;
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return 1;
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}
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return 0;
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}
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*/
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/* Start the FPGA programming by initialize the FPGA Manager */
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static int fpgamgr_program_init(void)
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{
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unsigned long msel, i;
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/* Get the MSEL value */
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msel = readl(&fpgamgr_regs->stat);
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msel &= FPGAMGRREGS_STAT_MSEL_MASK;
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msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
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/*
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* Set the cfg width
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* If MSEL[3] = 1, cfg width = 32 bit
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*/
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if (msel & 0x8) {
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setbits_le32(&fpgamgr_regs->ctrl,
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FPGAMGRREGS_CTRL_CFGWDTH_MASK);
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/* To determine the CD ratio */
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/* MSEL[1:0] = 0, CD Ratio = 1 */
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if ((msel & 0x3) == 0x0)
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fpgamgr_set_cd_ratio(CDRATIO_x1);
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/* MSEL[1:0] = 1, CD Ratio = 4 */
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else if ((msel & 0x3) == 0x1)
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fpgamgr_set_cd_ratio(CDRATIO_x4);
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/* MSEL[1:0] = 2, CD Ratio = 8 */
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else if ((msel & 0x3) == 0x2)
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fpgamgr_set_cd_ratio(CDRATIO_x8);
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}
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else { /* MSEL[3] = 0 */
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clrbits_le32(&fpgamgr_regs->ctrl,
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FPGAMGRREGS_CTRL_CFGWDTH_MASK);
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/* To determine the CD ratio */
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/* MSEL[1:0] = 0, CD Ratio = 1 */
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if ((msel & 0x3) == 0x0)
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fpgamgr_set_cd_ratio(CDRATIO_x1);
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/* MSEL[1:0] = 1, CD Ratio = 2 */
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else if ((msel & 0x3) == 0x1)
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fpgamgr_set_cd_ratio(CDRATIO_x2);
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/* MSEL[1:0] = 2, CD Ratio = 4 */
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else if ((msel & 0x3) == 0x2)
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fpgamgr_set_cd_ratio(CDRATIO_x4);
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}
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/* To enable FPGA Manager configuration */
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
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/* To enable FPGA Manager drive over configuration line */
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
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/* Put FPGA into reset phase */
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
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/* (1) wait until FPGA enter reset phase */
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
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break;
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}
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/* If not in reset state, return error */
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
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puts("FPGA: Could not reset\n");
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return -1;
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}
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/* Release FPGA from reset phase */
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
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/* (2) wait until FPGA enter configuration phase */
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
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break;
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}
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/* If not in configuration state, return error */
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
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puts("FPGA: Could not configure\n");
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return -2;
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}
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/* Clear all interrupts in CB Monitor */
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writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
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/* Enable AXI configuration */
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setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
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return 0;
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}
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#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
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/* Write the RBF data to FPGA Manager */
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static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
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{
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uint32_t src = (uint32_t)rbf_data;
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uint32_t dst = (uint32_t)MAP_ADDR(SOCFPGA_FPGAMGRDATA_ADDRESS);
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/* Number of loops for 32-byte long copying. */
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uint32_t loops32 = rbf_size / 32;
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/* Number of loops for 4-byte long copying + trailing bytes */
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uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
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__asm volatile(
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"1: ldmia %0!,{r0-r7} \n"
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" stmia %1!,{r0-r7} \n"
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" sub %1, #32 \n"
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" subs %2, #1 \n"
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" bne 1b \n"
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" cmp %3, #0 \n"
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" beq 3f \n"
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"2: ldr %2, [%0], #4 \n"
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" str %2, [%1] \n"
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" subs %3, #1 \n"
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" bne 2b \n"
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"3: nop \n"
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: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
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}
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/* Ensure the FPGA entering config done */
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static int fpgamgr_program_poll_cd(void)
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{
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const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
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FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
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unsigned long reg, i;
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/* (3) wait until full config done */
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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reg = readl(&fpgamgr_regs->gpio_ext_porta);
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/* Config error */
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if (!(reg & mask)) {
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printf("FPGA: Configuration error.\n");
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return -3;
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}
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/* Config done without error */
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if (reg & mask)
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break;
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}
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/* Timeout happened, return error */
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if (i == FPGA_TIMEOUT_CNT) {
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printf("FPGA: Timeout waiting for program.\n");
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return -4;
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}
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/* Disable AXI configuration */
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
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return 0;
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}
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/* Ensure the FPGA entering init phase */
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static int fpgamgr_program_poll_initphase(void)
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{
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unsigned long i;
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/* Additional clocks for the CB to enter initialization phase */
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if (fpgamgr_dclkcnt_set(0x4))
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return -5;
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/* (4) wait until FPGA enter init phase or user mode */
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
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break;
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
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break;
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}
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/* If not in configuration state, return error */
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if (i == FPGA_TIMEOUT_CNT)
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return -6;
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return 0;
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}
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/* Ensure the FPGA entering user mode */
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static int fpgamgr_program_poll_usermode(void)
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{
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unsigned long i;
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/* Additional clocks for the CB to exit initialization phase */
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if (fpgamgr_dclkcnt_set(0x5000))
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return -7;
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/* (5) wait until FPGA enter user mode */
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
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break;
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}
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/* If not in configuration state, return error */
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if (i == FPGA_TIMEOUT_CNT)
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return -8;
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/* To release FPGA Manager drive over configuration line */
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clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
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return 0;
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}
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/*
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* FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
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* Return 0 for sucess, non-zero for error.
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*/
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static int socfpga_load(const void *rbf_data, size_t rbf_size)
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{
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unsigned long status;
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if ((uint32_t)rbf_data & 0x3) {
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printf("FPGA: Unaligned data, realign to 32bit boundary.\n");
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return -EINVAL;
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}
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/* Initialize the FPGA Manager */
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status = fpgamgr_program_init();
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if (status)
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return status;
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/* Write the RBF data to FPGA Manager */
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fpgamgr_program_write(rbf_data, rbf_size);
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/* Ensure the FPGA entering config done */
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status = fpgamgr_program_poll_cd();
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if (status)
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return status;
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/* Ensure the FPGA entering init phase */
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status = fpgamgr_program_poll_initphase();
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if (status)
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return status;
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/* Ensure the FPGA entering user mode */
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return fpgamgr_program_poll_usermode();
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}
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static void do_bridge(uint32_t enable)
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{
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if (enable)
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{
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writel(0x00003FFF, (void*)(SOCFPGA_SDR_ADDRESS + 0x5080));
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writel(0x00000000, &reset_regs->brg_mod_reset);
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writel(0x00000019, &nic301_regs->remap);
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}
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else
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{
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writel(0, &sysmgr_regs->fpgaintfgrp_module);
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writel(0, (void*)(SOCFPGA_SDR_ADDRESS + 0x5080));
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writel(7, &reset_regs->brg_mod_reset);
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writel(1, &nic301_regs->remap);
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}
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}
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static int make_env(const char *name, const char *cfg)
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{
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if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) return -1;
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void* buf = mmap(0, 0x1000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x1FFFF000);
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if (buf == (void *)-1)
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{
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printf("Unable to mmap(/dev/mem)\n");
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close(fd);
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return -1;
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}
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volatile char* str = (volatile char*)buf;
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memset((void*)str, 0, 0xF00);
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*str++ = 0x21;
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*str++ = 0x43;
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*str++ = 0x65;
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*str++ = 0x87;
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*str++ = 'c';
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*str++ = 'o';
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*str++ = 'r';
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*str++ = 'e';
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*str++ = '=';
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*str++ = '"';
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for (uint32_t i = 0; i < strlen(name); i++)
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{
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*str++ = name[i];
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}
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*str++ = '"';
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*str++ = '\n';
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FileLoad(cfg, (void*)str, 0);
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munmap(buf, 0x1000);
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return 0;
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}
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int fpga_load_rbf(const char *name, const char *cfg)
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{
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OsdDisable();
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static char path[1024];
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int ret = 0;
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if(cfg)
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{
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make_env(name, cfg);
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do_bridge(0);
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reboot(0);
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}
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printf("Loading RBF: %s\n", name);
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if(name[0] == '/') strcpy(path, name);
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else sprintf(path, "%s/%s", !strcasecmp(name, "menu.rbf") ? getStorageDir(0) : getRootDir(), name);
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int rbf = open(path, O_RDONLY);
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if (rbf < 0)
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{
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printf("Couldn't open file %s\n", path);
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return -1;
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}
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else
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{
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struct stat64 st;
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if (fstat64(rbf, &st)<0)
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{
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printf("Couldn't get info of file %s\n", path);
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ret = -1;
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}
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else
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{
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printf("Bitstream size: %lld bytes\n", st.st_size);
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void *buf = malloc(st.st_size);
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if (!buf)
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{
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printf("Couldn't allocate %llu bytes.\n", st.st_size);
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ret = -1;
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}
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else
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{
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if (read(rbf, buf, st.st_size)<st.st_size)
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{
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printf("Couldn't read file %s\n", name);
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ret = -1;
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}
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else
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{
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void *p = buf;
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__off64_t sz = st.st_size;
|
|
if (!memcmp(buf, "MiSTer", 6))
|
|
{
|
|
sz = *(uint32_t*)(((uint8_t*)buf) + 12);
|
|
p = (void*)(((uint8_t*)buf) + 16);
|
|
}
|
|
do_bridge(0);
|
|
ret = socfpga_load(p, sz);
|
|
if (ret)
|
|
{
|
|
printf("Error %d while loading %s\n", ret, path);
|
|
}
|
|
else
|
|
{
|
|
do_bridge(1);
|
|
}
|
|
}
|
|
free(buf);
|
|
}
|
|
}
|
|
}
|
|
close(rbf);
|
|
app_restart(!strcasecmp(name, "menu.rbf") ? "menu.rbf" : path);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int fpga_io_init()
|
|
{
|
|
if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) return -1;
|
|
|
|
map_base = (uint32_t*)mmap(0, FPGA_REG_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, FPGA_REG_BASE);
|
|
if (map_base == (void *)-1)
|
|
{
|
|
printf("Unable to mmap(/dev/mem)\n");
|
|
close(fd);
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t gpo_copy = 0;
|
|
void fpga_gpo_write(uint32_t value)
|
|
{
|
|
gpo_copy = value;
|
|
writel(value, (void*)(SOCFPGA_MGR_ADDRESS + 0x10));
|
|
}
|
|
|
|
uint32_t fpga_gpo_read()
|
|
{
|
|
return gpo_copy; //readl((void*)(SOCFPGA_MGR_ADDRESS + 0x10));
|
|
}
|
|
|
|
int fpga_gpi_read()
|
|
{
|
|
return readl((void*)(SOCFPGA_MGR_ADDRESS + 0x14));
|
|
}
|
|
|
|
void fpga_core_write(uint32_t offset, uint32_t value)
|
|
{
|
|
if (offset <= 0x1FFFFF) writel(value, (void*)(SOCFPGA_LWFPGASLAVES_ADDRESS + (offset & ~3)));
|
|
}
|
|
|
|
uint32_t fpga_core_read(uint32_t offset)
|
|
{
|
|
if (offset <= 0x1FFFFF) return readl((void*)(SOCFPGA_LWFPGASLAVES_ADDRESS + (offset & ~3)));
|
|
return 0;
|
|
}
|
|
|
|
int fpga_core_id()
|
|
{
|
|
uint32_t gpo = (fpga_gpo_read() & 0x7FFFFFFF);
|
|
fpga_gpo_write(gpo);
|
|
uint32_t coretype = fpga_gpi_read();
|
|
gpo |= 0x80000000;
|
|
fpga_gpo_write(gpo);
|
|
|
|
if ((coretype >> 8) != 0x5CA623) return -1;
|
|
return coretype & 0xFF;
|
|
}
|
|
|
|
int fpga_get_fio_size()
|
|
{
|
|
return (fpga_gpi_read()>>16) & 1;
|
|
}
|
|
|
|
int fpga_get_io_version()
|
|
{
|
|
return (fpga_gpi_read() >> 18) & 3;
|
|
}
|
|
|
|
void fpga_set_led(uint32_t on)
|
|
{
|
|
uint32_t gpo = fpga_gpo_read();
|
|
fpga_gpo_write(on ? gpo | 0x20000000 : gpo & ~0x20000000);
|
|
}
|
|
|
|
int fpga_get_buttons()
|
|
{
|
|
fpga_gpo_write(fpga_gpo_read() | 0x80000000);
|
|
int gpi = fpga_gpi_read();
|
|
if (gpi < 0) gpi = 0; // FPGA is not in user mode. Ignore the data;
|
|
return (gpi >> 29) & 3;
|
|
}
|
|
|
|
int fpga_get_io_type()
|
|
{
|
|
fpga_gpo_write(fpga_gpo_read() | 0x80000000);
|
|
return (fpga_gpi_read() >> 28) & 1;
|
|
}
|
|
|
|
void reboot(int cold)
|
|
{
|
|
sync();
|
|
fpga_core_reset(1);
|
|
|
|
usleep(500000);
|
|
|
|
writel(cold ? 0 : 0x1, &reset_regs->tstscratch);
|
|
writel(2, &reset_regs->ctrl);
|
|
while (1);
|
|
}
|
|
|
|
char *getappname()
|
|
{
|
|
static char dest[PATH_MAX];
|
|
memset(dest, 0, sizeof(dest));
|
|
|
|
char path[64];
|
|
sprintf(path, "/proc/%d/exe", getpid());
|
|
readlink(path, dest, PATH_MAX);
|
|
|
|
return dest;
|
|
}
|
|
|
|
void app_restart(const char *path)
|
|
{
|
|
sync();
|
|
fpga_core_reset(1);
|
|
|
|
input_switch(0);
|
|
input_uinp_destroy();
|
|
|
|
char *appname = getappname();
|
|
printf("restarting the %s\n", appname);
|
|
execl(appname, appname, path, NULL);
|
|
|
|
printf("Something went wrong. Rebooting...\n");
|
|
reboot(0);
|
|
}
|
|
|
|
void fpga_core_reset(int reset)
|
|
{
|
|
uint32_t gpo = fpga_gpo_read() & ~0xC0000000;
|
|
fpga_gpo_write(reset ? gpo | 0x40000000 : gpo | 0x80000000);
|
|
}
|
|
|
|
int is_fpga_ready(int quick)
|
|
{
|
|
if (quick)
|
|
{
|
|
return (fpga_gpi_read() >= 0);
|
|
}
|
|
|
|
return fpgamgr_test_fpga_ready();
|
|
}
|