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sorgelig
141
fpga_system_manager.h
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141
fpga_system_manager.h
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYSTEM_MANAGER_H_
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#define _SYSTEM_MANAGER_H_
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struct socfpga_system_manager {
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/* System Manager Module */
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uint32_t siliconid1; /* 0x00 */
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uint32_t siliconid2;
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uint32_t _pad_0x8_0xf[2];
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uint32_t wddbg; /* 0x10 */
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uint32_t bootinfo;
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uint32_t hpsinfo;
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uint32_t parityinj;
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/* FPGA Interface Group */
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uint32_t fpgaintfgrp_gbl; /* 0x20 */
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uint32_t fpgaintfgrp_indiv;
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uint32_t fpgaintfgrp_module;
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uint32_t _pad_0x2c_0x2f;
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/* Scan Manager Group */
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uint32_t scanmgrgrp_ctrl; /* 0x30 */
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uint32_t _pad_0x34_0x3f[3];
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/* Freeze Control Group */
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uint32_t frzctrl_vioctrl; /* 0x40 */
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uint32_t _pad_0x44_0x4f[3];
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uint32_t frzctrl_hioctrl; /* 0x50 */
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uint32_t frzctrl_src;
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uint32_t frzctrl_hwctrl;
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uint32_t _pad_0x5c_0x5f;
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/* EMAC Group */
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uint32_t emacgrp_ctrl; /* 0x60 */
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uint32_t emacgrp_l3master;
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uint32_t _pad_0x68_0x6f[2];
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/* DMA Controller Group */
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uint32_t dmagrp_ctrl; /* 0x70 */
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uint32_t dmagrp_persecurity;
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uint32_t _pad_0x78_0x7f[2];
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/* Preloader (initial software) Group */
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uint32_t iswgrp_handoff[8]; /* 0x80 */
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uint32_t _pad_0xa0_0xbf[8]; /* 0xa0 */
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/* Boot ROM Code Register Group */
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uint32_t romcodegrp_ctrl; /* 0xc0 */
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uint32_t romcodegrp_cpu1startaddr;
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uint32_t romcodegrp_initswstate;
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uint32_t romcodegrp_initswlastld;
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uint32_t romcodegrp_bootromswstate; /* 0xd0 */
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uint32_t __pad_0xd4_0xdf[3];
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/* Warm Boot from On-Chip RAM Group */
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uint32_t romcodegrp_warmramgrp_enable; /* 0xe0 */
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uint32_t romcodegrp_warmramgrp_datastart;
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uint32_t romcodegrp_warmramgrp_length;
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uint32_t romcodegrp_warmramgrp_execution;
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uint32_t romcodegrp_warmramgrp_crc; /* 0xf0 */
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uint32_t __pad_0xf4_0xff[3];
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/* Boot ROM Hardware Register Group */
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uint32_t romhwgrp_ctrl; /* 0x100 */
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uint32_t _pad_0x104_0x107;
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/* SDMMC Controller Group */
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uint32_t sdmmcgrp_ctrl;
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uint32_t sdmmcgrp_l3master;
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/* NAND Flash Controller Register Group */
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uint32_t nandgrp_bootstrap; /* 0x110 */
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uint32_t nandgrp_l3master;
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/* USB Controller Group */
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uint32_t usbgrp_l3master;
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uint32_t _pad_0x11c_0x13f[9];
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/* ECC Management Register Group */
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uint32_t eccgrp_l2; /* 0x140 */
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uint32_t eccgrp_ocram;
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uint32_t eccgrp_usb0;
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uint32_t eccgrp_usb1;
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uint32_t eccgrp_emac0; /* 0x150 */
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uint32_t eccgrp_emac1;
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uint32_t eccgrp_dma;
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uint32_t eccgrp_can0;
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uint32_t eccgrp_can1; /* 0x160 */
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uint32_t eccgrp_nand;
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uint32_t eccgrp_qspi;
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uint32_t eccgrp_sdmmc;
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uint32_t _pad_0x170_0x3ff[164];
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/* Pin Mux Control Group */
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uint32_t emacio[20]; /* 0x400 */
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uint32_t flashio[12]; /* 0x450 */
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uint32_t generalio[28]; /* 0x480 */
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uint32_t _pad_0x4f0_0x4ff[4];
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uint32_t mixed1io[22]; /* 0x500 */
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uint32_t mixed2io[8]; /* 0x558 */
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uint32_t gplinmux[23]; /* 0x578 */
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uint32_t gplmux[71]; /* 0x5d4 */
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uint32_t nandusefpga; /* 0x6f0 */
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uint32_t _pad_0x6f4;
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uint32_t rgmii1usefpga; /* 0x6f8 */
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uint32_t _pad_0x6fc_0x700[2];
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uint32_t i2c0usefpga; /* 0x704 */
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uint32_t sdmmcusefpga; /* 0x708 */
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uint32_t _pad_0x70c_0x710[2];
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uint32_t rgmii0usefpga; /* 0x714 */
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uint32_t _pad_0x718_0x720[3];
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uint32_t i2c3usefpga; /* 0x724 */
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uint32_t i2c2usefpga; /* 0x728 */
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uint32_t i2c1usefpga; /* 0x72c */
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uint32_t spim1usefpga; /* 0x730 */
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uint32_t _pad_0x734;
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uint32_t spim0usefpga; /* 0x738 */
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};
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
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#define SYSMGR_ECC_OCRAM_EN (1 << 0)
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#define SYSMGR_ECC_OCRAM_SERR (1 << 3)
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#define SYSMGR_ECC_OCRAM_DERR (1 << 4)
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#define SYSMGR_FPGAINTF_USEFPGA 0x1
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#define SYSMGR_FPGAINTF_SPIM0 (1 << 0)
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#define SYSMGR_FPGAINTF_SPIM1 (1 << 1)
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#define SYSMGR_FPGAINTF_EMAC0 (1 << 2)
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#define SYSMGR_FPGAINTF_EMAC1 (1 << 3)
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#define SYSMGR_FPGAINTF_NAND (1 << 4)
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#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
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#else
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
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#endif
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#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
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/* EMAC Group Bit definitions */
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
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#endif /* _SYSTEM_MANAGER_H_ */
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