diff --git a/.gitignore b/.gitignore index a5d12ce..9a077eb 100644 --- a/.gitignore +++ b/.gitignore @@ -50,4 +50,9 @@ software/roms/cbios_bank6.rom software/roms/cbios_bank7.rom software/roms/cbios_bank8.rom software/src/sdtest.c +software/CPM/tools/ +software/asm/rfs_bank2.prewriteread +software/roms/SHARP_MZ80A_RFS_CPM_IMAGE_1.img +software/roms/SHARP_MZ80A_RFS_IMAGE_1.img +software/roms/cmp diff --git a/software/MZF/cpm22.MZF b/software/MZF/cpm22.MZF index c9ed822..d9c1baf 100644 Binary files a/software/MZF/cpm22.MZF and b/software/MZF/cpm22.MZF differ diff --git a/software/asm/cbios.asm b/software/asm/cbios.asm index 87629c6..9cc7e0c 100644 --- a/software/asm/cbios.asm +++ b/software/asm/cbios.asm @@ -12,7 +12,10 @@ ;- come from the Z80-MBC2 project, (C) SuperFabius. ;- Copyright: (c) 2018-20 Philip Smart ;- -;- History: January 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +;- History: Jan 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +; May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the +; additional and different hardware. The SPI is now onboard the PCB and +; not using the printer interface card. ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify ;- it under the terms of the GNU General Public License as published @@ -64,25 +67,25 @@ ; CBIOS Bank 1 - Utilities and Audio. BANK8: PUSH AF LD A,ROMBANK8 - LD (RFSBK2),A + LD (BNKSELUSER),A POP AF RET ; CBIOS Bank 2 - Screen / ANSI Terminal BANK9: PUSH AF LD A,ROMBANK9 - LD (RFSBK2),A + LD (BNKSELUSER),A POP AF RET ; CBIOS Bank 3 - SD Card. BANK10: PUSH AF LD A,ROMBANK10 - LD (RFSBK2),A + LD (BNKSELUSER),A POP AF RET ; CBIOS Bank 4 BANK11: PUSH AF LD A,ROMBANK11 - LD (RFSBK2),A + LD (BNKSELUSER),A POP AF RET @@ -102,7 +105,7 @@ BANKTOBANK_:LD (USRBANKSAV),A ; Save SRL A SRL A SRL A - LD (RFSBK2),A + LD (BNKSELUSER),A LD (HLSAVE),HL ; Save HL (exec address) whilst we get AF from stack. POP HL ; HL = return address in original bank. POP AF ; AF to pass to called routine. @@ -114,15 +117,16 @@ BANKTOBANK_:LD (USRBANKSAV),A ; Save BKTOBKRET: PUSH AF LD A,(USRBANKSAV) AND 00FH ; We just want the bank number we are returning to. - LD (RFSBK2),A ; Switch back bank. + LD (BNKSELUSER),A ; Switch back bank. POP AF ; Restore A and flags to pass back to caller. RET ; Public methods for User Rom CBIOS Bank 1 - Utility functions. ?REBOOT: LD A,ROMBANK8 ; Method to exit CPM and return to the Sharp MZ80A Monitor. - LD (RFSBK2),A - JP QREBOOT + SCF + CALL SELUSRBNK ; Ensure Rom Control is enabled + JP QREBOOT ; Reboot has to take place from User ROM as the monitor ROM is swapped back to default position. ?MLDY: CALL BANK8 ; Method to sound a melody given an input array of notes to play. JP QMELDY @@ -236,7 +240,7 @@ BKTOBKRET: PUSH AF ; in the header at $1108 to ensure correct startup. ; LD A,($E00C) ; - Switch ROM to location $C000 ; LD A,ROMBANK2 ; - Switch to the CBIOS rom in bank 2 of the monitor rom bank. - ; LD ($EFFC),A ; - Perform the bank switch. + ; LD ($EFFD),A ; - Perform the bank switch. ; JP $C000 ; - Go to BOOT_ ;------------------------------------------------------------------------------- BOOT_: LD SP,BIOSSTACK @@ -631,6 +635,29 @@ ALLOC2: LD (RSFLAG), A ; rsfla LD SP,(SPSAVE) ; Restore the CPM stack. RET + + ; Function to select a User Bank. If Carry is clear upon entry, on exit the control registers will be disabled. If carry is set then the control registers are left active. + ; During normal operations the control registers are enabled. When access is needed to the full User ROM space, ie for drive read/write then the registers are disabled after + ; setting the correct bank. + ; +SELUSRBNK: PUSH BC + PUSH AF + LD A,(ROMCTL) ; Get current setting for the coded latch, ie. number of reads needed to enable it. + RRA + RRA + CPL + AND 00FH ; Preserve bits 3-1, bit 0 is always 0 on the 74HCT191 latch. + LD B,A ; Set value to B for loop. + LD A,(BNKCTRLDIS) +SELUSRBNK1: LD A,(BNKSELUSER) + DJNZ SELUSRBNK1 + POP AF + POP BC + LD (BNKSELUSER),A ; Select the required bank. + JR C,SELUSRBNK2 ; If Carry is set by caller then leave the control registers active. + LD (BNKCTRLDIS),A ; Disable the control registers, value of A is not important. +SELUSRBNK2: RET + ;------------------------------------------------------------------------------- ; INIT ; @@ -638,6 +665,7 @@ ALLOC2: LD (RSFLAG), A ; rsfla ;------------------------------------------------------------------------------- INIT: DI IM 1 + ; LD HL,VARSTART ; Start of variable area LD BC,VAREND-VARSTART ; Size of variable area. XOR A @@ -649,7 +677,18 @@ INIT: DI LD HL,ARAM STRT1: CALL CLR8 LD A,004H - LD (TEMPW),A + LD (TEMPW),A ; Setup the tempo for sound output. + + ; Initialise the Rom Paging Control Registers. + LD B,16 ; If we read the bank control reset register 16 times then this will enable bank control and the 16th read will reset all bank control registers to default. +INIT1: LD A,(BNKCTRLRST) + DJNZ INIT1 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + LD (ROMCTL),A ; Save to memory the value in the bank control register - this register is used for SPI etc so need to remember its setting. + LD A,ROMBANK9 ; Screen Bank. + LD (BNKSELUSER),A + ; ; Setup keyboard buffer control. LD A,0 @@ -676,10 +715,9 @@ STRT1: CALL CLR8 LD (DSPCTL), A CALL ?MLDSP CALL ?NL - LD DE,CBIOSSIGNON + LD DE,CBIOSSIGNON ; Start of sign on message, as devices are detected they are added to the sign on. CALL MONPRTSTR - CALL ?NL - CALL ?BEL + CALL ?BEL ; Beep to indicate startup - for cases where screen is slow to startup. LD A,0FFH LD (SWRK),A @@ -687,12 +725,20 @@ STRT1: CALL CLR8 ; Initialise the SD Card subsystem (if connected). ; CALL ?SDINIT - LD A,(DRVAVAIL) - SET 2,A ; Assume the SD Card is present. - JR Z,STRT2 + LD A,0 ; No drives yet detected so zero available mask. RES 2,A ; No SD Card is present. + JR NZ,STRT2 + SET 2,A ; Assume the SD Card is present. + ; + PUSH AF ; Output indicator that SDC drives are available. + LD DE,SDAVAIL + CALL MONPRTSTR + POP AF + SET 7,A + ; ; Locate the CPM Image and store the Bank/Block to speed up warm boot. STRT2: LD (DRVAVAIL),A + ; LD HL,CPMROMFNAME ; Name of CPM File in rom. CALL FINDMZF JP NZ,ROMFINDERR ; Failed to find CPM in the ROM! This shouldnt happen as we boot from ROM. @@ -708,16 +754,36 @@ STRT2: LD (DRVAVAIL),A LD (CPMROMDRV0),BC ; If found store the bank and page the image is located at. LD A,(DRVAVAIL) SET 1,A ; Indicate ROM drives are available. + ; + PUSH AF ; Output indicator that ROM 1 drive is available. + BIT 7,A + JR Z,STRT2A + LD A,',' + CALL ?PRNT +STRT2A: LD DE,ROM1AVAIL + CALL MONPRTSTR + POP AF + SET 7,A LD (DRVAVAIL),A - + ; STRT3: LD HL,CPMRDRVFN1 ; Name of CPM Rom Drive File 1 in rom. CALL FINDMZF JR NZ,STRT4 ; Failed to find the drive image in the ROM! LD (CPMROMDRV1),BC ; If found store the bank and page the image is located at. LD A,(DRVAVAIL) SET 1,A ; Indicate ROM drives are available. + ; + PUSH AF ; Output indicator that ROM 2 drive is available. + BIT 7,A + JR Z,STRT3A + LD A,',' + CALL ?PRNT +STRT3A: LD DE,ROM2AVAIL + CALL MONPRTSTR + POP AF + SET 7,A LD (DRVAVAIL),A - + ; STRT4: LD HL,NUMBERBUF LD (NUMBERPOS),HL ; @@ -729,9 +795,23 @@ STRT4: LD HL,NUMBERBUF JR NZ,STRT5 LD A,(DRVAVAIL) SET 0,A ; Indicate Floppy drives are available. - LD (DRVAVAIL),A -STRT5: LD DE,DPBASE ; Base of parameter block. + PUSH AF ; Output indicator that FDC drives are available. + BIT 7,A + JR Z,STRT4A + LD A,',' + CALL ?PRNT +STRT4A: LD DE,FDCAVAIL + CALL MONPRTSTR + POP AF + SET 7,A + LD (DRVAVAIL),A + ; +STRT5: LD DE,CBIOSIGNEND ; Terminate the signon message which now includes list of drives detected. + CALL MONPRTSTR + CALL ?NL + ; + LD DE,DPBASE ; Base of parameter block. LD A,0 ; Using scratch area, setup the disk count, pointer to ALV memory and pointer to CSV memory. LD (CDIRBUF),A LD HL,CSVALVMEM @@ -807,8 +887,6 @@ STRT10: LD A,(CDIRBUF) LD DE,00000H LD HL,00000H CALL ?TIMESET - - EI ; JR CPMINIT @@ -860,13 +938,12 @@ COPYDPB1: LDI ; required, reinitialise any needed hardware and reload CCP+BDOS. ;------------------------------------------------------------------------------- WINIT: DI - ; Reload the CCP and BDOS from ROM. LD DE,CPMBIOS-CBASE ; Only want to load in CCP and BDOS. LD BC,(CPMROMLOC) ; Load up the Bank and Page where the CPM Image can be found. CALL UROMLOAD LD A,ROMBANK9 ; Screen Bank. - LD (RFSBK2),A + LD (BNKSELUSER),A ; CPMINIT: LD A,(DRVAVAIL) BIT 0,A @@ -1378,7 +1455,8 @@ FINDMZF0: LD B,USRROMPAGES ; First 16 pages are reserved in LD C,0 ; Block in page. LD D,0 ; File numbering start. FINDMZF1: LD A,B - LD (RFSBK2), A ; Select bank. + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK FINDMZF2: PUSH BC ; Preserve bank count/block number. PUSH DE ; Preserve file numbering. LD HL,0E800h + RFS_ATRB ; Add block offset to get the valid block. @@ -1419,20 +1497,24 @@ FINDMZF5: LD A,B JR FINDMZFNO FINDMZFYES: ; Z Flag set by previous test. -FINDMZFNO: RET +FINDMZFNO: LD A,ROMBANK9 + SCF ; Select the required user bank and Set carry so that the control registers remain enabled. + CALL SELUSRBNK + RET - ; Load Program from ROM - ; IN BC Bank and Block of MZF file. - ; DE 0 - use file size in header, > 0 file size to load. - ; OUT zero Set if file loaded, reset if an error occurred. - ; - ; Load program from RFS Bank 2 (User ROM Bank) - ; + ; Load Program from ROM + ; IN BC Bank and Block of MZF file. + ; DE 0 - use file size in header, > 0 file size to load. + ; OUT zero Set if file loaded, reset if an error occurred. + ; + ; Load program from RFS Bank 2 (User ROM Bank) + ; UROMLOAD: PUSH BC PUSH DE LD A,B - LD (RFSBK2), A + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK ; LD DE, IBUFE ; Copy the header into the work area. LD HL, 0E800h ; Add block offset to get the valid block. @@ -1469,7 +1551,8 @@ LROMLOAD1: PUSH HL ; B = Bank ; C = Block LROMLOAD2: LD A, B - LD (RFSBK2), A + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK LROMLOAD3: PUSH BC LD HL, 0E800h @@ -1523,7 +1606,8 @@ LROMLOAD7: LD A, B LROMLOAD8: POP BC LROMLOAD5: PUSH AF LD A,ROMBANK9 - LD (RFSBK2), A ; Set the MROM bank back to original. + SCF ; Select the required user bank and Set carry so that the control registers remain enabled. + CALL SELUSRBNK POP AF RET @@ -1612,7 +1696,8 @@ ROMREAD11: DJNZ ROMREAD10 LD C,A LD B,E ; Currently only 8bit bank number, store in B. LD A, E - LD (RFSBK2), A ; Starting bank. + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK PUSH BC PUSH HL LD DE,HSTBUF ; Target is the host buffer. @@ -1624,7 +1709,8 @@ ROMREAD11: DJNZ ROMREAD10 ; B = Bank ; C = Block ROMREAD12: LD A, B - LD (RFSBK2), A + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK ; LD A,H ; If we reach the top of the user rom space, wrap around. CP FDCROMADDR / 0100H ; Compare high byte against high byte of floppy rom. @@ -1671,9 +1757,10 @@ ROMREAD16: LD A, B ROMREAD17: POP BC ROMREAD18: PUSH AF LD A,ROMBANK9 ; Reselect utilities bank. - LD (RFSBK2), A ; Set the MROM bank back to original. + SCF ; Select the required user bank and Set carry so that the control registers remain enabled. + CALL SELUSRBNK POP AF - POP HL + POP HL ; HL/BC pushed onto stack in READHST, a jump was made this method not a call. POP BC RET @@ -2451,13 +2538,18 @@ KTBLC: ; CTRL ON -CBIOSSIGNON:DB "** CBIOS v1.11, (C) P.D. Smart, 2020 **", CR, NUL -CPMSIGNON: DB "CP/M v2.23 (48K) COPYRIGHT(C) 1979, DIGITAL RESEARCH",CR, LF, NUL -CPMROMFNAME:DB "CPM223", NUL -CPMRDRVFN0: DB "CPM22-DRV0", NUL -CPMRDRVFN1: DB "CPM22-DRV1", NUL -ROMLDERRMSG:DB "ROM LOAD", CR, NUL -ROMFDERRMSG:DB "ROM FIND", CR, NUL +CBIOSSIGNON:DB "** CBIOS v1.20, (C) P.D. Smart, 2020. Drives:", NUL +CBIOSIGNEND:DB " **", CR, NUL +CPMSIGNON: DB "CP/M v2.23 (48K) COPYRIGHT(C) 1979, DIGITAL RESEARCH", CR, LF, NUL +CPMROMFNAME:DB "CPM223", NUL +CPMRDRVFN0: DB "CPM22-DRV0", NUL +CPMRDRVFN1: DB "CPM22-DRV1", NUL +ROMLDERRMSG:DB "ROM LOAD ERR", CR, NUL +ROMFDERRMSG:DB "ROM FIND ERR", CR, NUL +SDAVAIL: DB "SD", NUL +ROM1AVAIL: DB "ROM1", NUL +ROM2AVAIL: DB "ROM2", NUL +FDCAVAIL: DB "FDC", NUL ;------------------------------------------------------------------------------- ; END OF STATIC LOOKUP TABLES AND CONSTANTS diff --git a/software/asm/cbios_bank1.asm b/software/asm/cbios_bank1.asm index d37254f..bcadce4 100644 --- a/software/asm/cbios_bank1.asm +++ b/software/asm/cbios_bank1.asm @@ -1,7 +1,7 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: cbios_bank1.asm -;- Created: October 2018 +;- Created: January 2020 ;- Author(s): Philip Smart ;- Description: Sharp MZ series CPM BIOS System. ;- This assembly language program is written to utilise the banked flashroms added with @@ -11,7 +11,10 @@ ;- Credits: ;- Copyright: (c) 2018-20 Philip Smart ;- -;- History: January 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +;- History: Jan 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +; May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the +; additional and different hardware. The SPI is now onboard the PCB and +; not using the printer interface card. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -39,26 +42,40 @@ ; Common code spanning all banks to ensure that a Monitor is selected upon power up/reset. ;----------------------------------------------------------------------------------------- NOP - XOR A ; We shouldnt arrive here after a reset, ensure MROM and UROM are set to bank 0 - LD (RFSBK1),A ; then a restart will take place as Bank 0 will jump to vector 00000H - LD (RFSBK2),A + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +CBIOS1_0: LD A,(BNKCTRLRST) + DJNZ CBIOS1_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A NOP - ; After switching in Bank 0, it will automatically continue processing in Bank 0 at the XOR A instructionof ROMFS: + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. + ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + ;------------------------------------------------------------------------------- ; Jump table for entry into this pages functions. ;------------------------------------------------------------------------------- - JP ?REBOOT ; 9 REBOOT - JP ?MLDY ; 12 QMELDY - JP ?TEMP ; 15 QTEMP - JP MLDST ; 18 QMSTA - JP MLDSP ; 21 QMSTP - JP ?BEL ; 24 QBEL - JP ?MODE ; 27 QMODE - JP ?TIMESET ; 30 QTIMESET - JP ?TIMEREAD ; 33 QTIMEREAD - JP ?CHKKY ; 36 QCHKKY - JP ?GETKY ; 39 QGETKY + ALIGN_NOPS UROMJMPTBL + JP ?REBOOT ; REBOOT + JP ?MLDY ; QMELDY + JP ?TEMP ; QTEMP + JP MLDST ; QMSTA + JP MLDSP ; QMSTP + JP ?BEL ; QBEL + JP ?MODE ; QMODE + JP ?TIMESET ; QTIMESET + JP ?TIMEREAD ; QTIMEREAD + JP ?CHKKY ; QCHKKY + JP ?GETKY ; QGETKY diff --git a/software/asm/cbios_bank2.asm b/software/asm/cbios_bank2.asm index d2ece1e..152d31c 100644 --- a/software/asm/cbios_bank2.asm +++ b/software/asm/cbios_bank2.asm @@ -9,10 +9,15 @@ ;- CPM TPA programs. ;- ;- Credits: ANSITERM utilises a heavily customised version of Ewen McNeill's Amstrad CPC EwenTerm +; Ansi Parser. +; ; (C) Oct 2000 - only the ansiterm.22b module was used with a lot stripped out. ;- Copyright: (c) 2018-20 Philip Smart ;- -;- History: January 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +;- History: Jan 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +; May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the +; additional and different hardware. The SPI is now onboard the PCB and +; not using the printer interface card. ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify ;- it under the terms of the GNU General Public License as published @@ -39,19 +44,33 @@ ; Common code spanning all banks to ensure that a Monitor is selected upon power up/reset. ;----------------------------------------------------------------------------------------- NOP - XOR A ; We shouldnt arrive here after a reset, ensure MROM and UROM are set to bank 0 - LD (RFSBK1),A ; then a restart will take place as Bank 0 will jump to vector 00000H - LD (RFSBK2),A + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +CBIOS2_0: LD A,(BNKCTRLRST) + DJNZ CBIOS2_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A NOP - ; After switching in Bank 0, it will automatically continue processing in Bank 0 at the XOR A instructionof ROMFS: + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. + ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + ;------------------------------------------------------------------------------- ; Jump table for entry into this pages functions. ;------------------------------------------------------------------------------- - JP ?PRNT ; 9 QPRNT - JP ?PRTHX ; 12 QPRTHX - JP ?PRTHL ; 15 QPRTHL - JP ?ANSITERM ; 18 QANSITERM + ALIGN_NOPS UROMJMPTBL + JP ?PRNT ; QPRNT + JP ?PRTHX ; QPRTHX + JP ?PRTHL ; QPRTHL + JP ?ANSITERM ; QANSITERM ;------------------------------------------------------------------------------- ; START OF SCREEN FUNCTIONALITY diff --git a/software/asm/cbios_bank3.asm b/software/asm/cbios_bank3.asm index 49337e0..3b505ea 100644 --- a/software/asm/cbios_bank3.asm +++ b/software/asm/cbios_bank3.asm @@ -1,7 +1,7 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: cbios_bank3.asm -;- Created: October 2018 +;- Created: January 2020 ;- Author(s): Philip Smart ;- Description: Sharp MZ series CPM BIOS System. ;- This assembly language program is written to utilise the banked flashroms added with @@ -11,7 +11,10 @@ ;- Credits: ;- Copyright: (c) 2018-20 Philip Smart ;- -;- History: January 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +;- History: Jan 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +; May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the +; additional and different hardware. The SPI is now onboard the PCB and +; not using the printer interface card. ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify ;- it under the terms of the GNU General Public License as published @@ -38,38 +41,68 @@ ; Common code spanning all banks to ensure that a Monitor is selected upon power up/reset. ;----------------------------------------------------------------------------------------- NOP - XOR A ; We shouldnt arrive here after a reset, ensure MROM and UROM are set to bank 0 - LD (RFSBK1),A ; then a restart will take place as Bank 0 will jump to vector 00000H - LD (RFSBK2),A + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +CBIOS3_0: LD A,(BNKCTRLRST) + DJNZ CBIOS3_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A NOP - ; After switching in Bank 0, it will automatically continue processing in Bank 0 at the XOR A instructionof ROMFS: + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. + ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + ;------------------------------------------------------------------------------- ; Jump table for entry into this pages functions. ;------------------------------------------------------------------------------- - JP ?SD_INIT ; 9 SD_INIT - JP ?SD_READ ; 12 SD_READ - JP ?SD_WRITE ; 15 SD_WRITE - JP ?SD_GETLBA ; 18 SD_GETLBA - JP ?SDC_READ ; 21 SDC_READ - JP ?SDC_WRITE ; 24 SDC_WRITE + ALIGN_NOPS UROMJMPTBL + JP ?SD_INIT ; SD_INIT + JP ?SD_READ ; SD_READ + JP ?SD_WRITE ; SD_WRITE + JP ?SD_GETLBA ; SD_GETLBA + JP ?SDC_READ ; SDC_READ + JP ?SDC_WRITE ; SDC_WRITE ;------------------------------------------------------------------------------- ; START OF SD CARD CONTROLLER FUNCTIONALITY ;------------------------------------------------------------------------------- + ;------------------------------------------------------------------------------- + ; Hardware SPI SD Controller (HW_SPI_ENA = 1) + ; This logic uses the RFS PCB v2+ hardware shift registers to communicate with + ; an SD Card. It is the fastest solution available but has a high IC count. + ; + ; Software SPI SD Controller (SW_SPI_ENA = 1) + ; This logic uses the RFS PCB v2+ logic to simulate the SPI interface with + ; bitbanging techniques. It is similar to the Parallel Port SD Controller + ; but uses logic on the RFS board rather than the parallel port interface. + ; + ; Parallel Port SD Controller (PP_SPI_ENA = 1) + ; This logic uses the standard Sharp MZ-80A Parallel Port for simulating the + ; SPI interface with bitbanging techniques. This interface is then used to + ; communicate with an SD Card. + ;------------------------------------------------------------------------------- + ; Method to initialise the SD card. ; -?SD_INIT: LD A,000H ; CS to high +?SD_INIT: LD A,0FFH ; CS to high (inactive) CALL SPICS ; CALL SPIINIT ; Train SD with our clock. ; - LD A,0FFH ; CS to low + LD A,000H ; CS to low (active) CALL SPICS - LD BC,0FFFFH + LD BC,01FFFH ; Number of retries before deciding card is not present. SD_INIT1: LD A,CMD0 ; Command 0 LD HL,00000H ; NB. Important, HL should be coded as LH due to little endian and the way it is used in SDCMD. LD DE,00000H ; NB. Important, DE should be coded as ED due to little endian and the way it is used in SDCMD. @@ -177,28 +210,6 @@ SD_INIT14: XOR A SD_EXIT: OR A ; Return value is in A. RET - ; Method to initialise communications with the SD card. We basically train it to our clock characteristics. - ; This is important, as is maintaining the same clock for read or write otherwise the card may not respond. -SPIINIT: LD B,80 -SPIINIT1: LD A,DOUT_HIGH | CLOCK_HIGH | CS_HIGH ; Output a 1 - OUT (SPI_OUT),A - LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH ; Output a 1 - OUT (SPI_OUT),A - DJNZ SPIINIT1 - RET - - ; Method to set the Chip Select level on the SD card. The Chip Select is active LOW. - ; - ; A = 0 - Set CS HIGH - ; A = 0xFF - Set CS LOW -SPICS: OR A - LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH ; Set CS High if parameter = 0 (ie. disable) - JR Z, SPICS0 - LD A,DOUT_HIGH | CLOCK_LOW | CS_LOW ; Set CS Low if parameter != 0 (ie. disable) -SPICS0: OUT (SPI_OUT),A - RET - - ; Method to send a command to the card and receive back a response. ; ; A = CMD to send ; LHED = Argument, ie. CMD = A, L, H, E, D, CRC @@ -309,46 +320,147 @@ SDACMD3: POP BC ; Succe XOR A RET + + + ; Method to initialise communications with the SD card. We basically train it to our clock characteristics. + ; This is important, as is maintaining the same clock for read or write otherwise the card may not respond. +SPIINIT: IF HW_SPI_ENA = 1 + ; Hardware SPI on the RFS v2+ PCB. + LD B,10 + LD A, 0FFH ; We need to send 80 '1's, so preload the data register with all 1's, future transmits dont require this as it self loads with 1's. + LD (HWSPIDATA),A +SPIINIT1: LD (HWSPISTART),A ; Commence transmission of an 8bit byte. Runs 1 8MHz, so 1 byte in 1uS, it takes the Z80 2uS for its quickest instruction at 2MHz clock. + DJNZ SPIINIT1 + RET + + ELSE + + ; Software SPI on the RFS v2+ PCB. + IF SW_SPI_ENA = 1 + + ELSE + + ; Software SPI on the centronics parallel port. + LD B,80 +SPIINIT1: LD A,DOUT_HIGH | CLOCK_HIGH | CS_HIGH ; Output a 1 + OUT (SPI_OUT),A + LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH ; Output a 1 + OUT (SPI_OUT),A + DJNZ SPIINIT1 + RET + ENDIF + ENDIF + + ; Method to set the Chip Select level on the SD card. The Chip Select is active LOW. + ; + ; A = 0 - Set CS LOW (active) + ; A = 0xFF - Set CS HIGH (active) +SPICS: IF HW_SPI_ENA = 1 + ; Hardware SPI on the RFS v2+ PCB. + OR A + LD A,(ROMCTL) + SET 1,A ; If we are inactivating CS then set CS high and disable clock by setting BBCLK to low. + RES 0,A + JR NZ, SPICS0 + RES 1,A ; If we are activating CS then set CS low and enable clock by setting BBCLK to high. + SET 0,A +SPICS0: LD (BNKCTRL),A + LD (ROMCTL),A + RET + + ELSE + + ; Software SPI on the RFS v2+ PCB. + IF SW_SPI_ENA = 1 + + ELSE + + ; Software SPI on the centronics parallel port. + OR A + LD A,DOUT_HIGH | CLOCK_LOW | CS_LOW ; Set CS Low if parameter = 0 (ie. enable) + JR Z, SPICS0 + LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH ; Set CS High if parameter != 0 (ie. disable) +SPICS0: OUT (SPI_OUT),A + RET + ENDIF + ENDIF + ; Method to send a byte to the SD card via the SPI protocol. - ; This method uses the bitbang technique, change if hardware spi is available. + ; This method uses the hardware shift registers. ; ; Input A = Byte to send. ; -SPIOUT: RLCA ; 65432107 - RLCA ; 54321076 - RLCA ; 43210765 - Adjust so that starting bit is same position as Data line. - LD E,A ; E = Character to send. - LD B,8 ; B = Bit count -SPIOUT0: LD A,E - AND DOUT_MASK ; Data bit to data line, clock and cs low. - RLC E -SPIOUT1: OUT (SPI_OUT),A - OR CLOCK_HIGH ; Clock high - OUT (SPI_OUT),A - AND CLOCK_MASK ; Clock low - OUT (SPI_OUT),A - DJNZ SPIOUT0 ; Perform actions for the full 8 bits. - RET +SPIOUT: IF HW_SPI_ENA = 1 + ; Hardware SPI on the RFS v2+ PCB. + LD (HWSPIDATA),A + LD (HWSPISTART),A + RET + + ELSE + + ; Software SPI on the RFS v2+ PCB. + IF SW_SPI_ENA = 1 + + ELSE + + ; Software SPI on the centronics parallel port. + RLCA ; 65432107 + RLCA ; 54321076 + RLCA ; 43210765 - Adjust so that starting bit is same position as Data line. + LD E,A ; E = Character to send. + LD B,8 ; B = Bit count +SPIOUT0: LD A,E + AND DOUT_MASK ; Data bit to data line, clock and cs low. + RLC E +SPIOUT1: OUT (SPI_OUT),A + OR CLOCK_HIGH ; Clock high + OUT (SPI_OUT),A + AND CLOCK_MASK ; Clock low + OUT (SPI_OUT),A + DJNZ SPIOUT0 ; Perform actions for the full 8 bits. + RET + ENDIF + ENDIF ; Method to receive a byte from the SD card via the SPI protocol. - ; This method uses the bitbang technique, change if hardware spi is available. + ; This method uses the hardware shift registers. ; NB. Timing must be very similar in SPIOUT and SPIIN. ; ; Output: A = received byte. ; -SPIIN: LD BC,00800H | SPI_OUT ; B = Bit count, C = clock port - LD L,0 ; L = Character being read. - LD D,DOUT_HIGH | CLOCK_LOW | CS_LOW ; Output a 0 - OUT (C),D ; To start ensure clock is low and CS is low. - LD E,DOUT_HIGH | CLOCK_HIGH | CS_LOW ; Output a 0 -SPIIN1: OUT (C),E ; Clock to high. - IN A,(SPI_IN) ; Input the received bit - OUT (C),D ; Clock to low. - SRL A - RL L - DJNZ SPIIN1 ; Perform actions for the full 8 bits. - LD A,L ; return value - RET +SPIIN: IF HW_SPI_ENA = 1 + ; Hardware SPI on the RFS v2+ PCB. + LD (HWSPISTART),A ; Commence transmission to receive back data from the SD card, we just send 1's. + LD A,(HWSPIDATA) ; Get the data byte. + RET + + ELSE + + ; Software SPI on the RFS v2+ PCB. + IF SW_SPI_ENA = 1 + + ELSE + + ; Software SPI on the centronics parallel port. + LD BC,00800H | SPI_OUT ; B = Bit count, C = clock port + LD L,0 ; L = Character being read. + LD D,DOUT_HIGH | CLOCK_LOW | CS_LOW ; Output a 0 + OUT (C),D ; To start ensure clock is low and CS is low. + LD E,DOUT_HIGH | CLOCK_HIGH | CS_LOW ; Output a 0 +SPIIN1: OUT (C),E ; Clock to high. + IN A,(SPI_IN) ; Input the received bit + OUT (C),D ; Clock to low. + SRL A + RL L + DJNZ SPIIN1 ; Perform actions for the full 8 bits. + LD A,L ; return value + RET + ENDIF + ENDIF + ;------------------------------------------------------------------------------- + ; End of SPI SD Controller + ;------------------------------------------------------------------------------- + ; A function from the z88dk stdlib, a delay loop with T state accuracy. ; @@ -430,7 +542,7 @@ LBATOADDR: LD HL,(SDSTARTSEC+1) ; Output: A = 0 - All ok. A > 0 - error occurred. ; ?SD_READ: PUSH HL ; Store the load address. - LD A,0 + LD A,000H CALL SPICS ; Set CS low (active). LD HL,(SDCAP) ; Test to see if CT_BLOCK is available. @@ -489,7 +601,7 @@ SD_READ4: PUSH HL ; Start LD A,0 ; And exit with success. SD_READ5: PUSH AF - LD A,0 + LD A,0FFH ; Disable CS therefore deselecting the SD Card. CALL SPICS POP AF RET @@ -505,7 +617,7 @@ SD_READ6: POP HL ; Output: A = 0 - All ok. A > 0 - error occurred. ?SD_WRITE: PUSH HL - LD A,0FFH ; Activate CS (set low). + LD A,000H ; Activate CS (set low). CALL SPICS ; Open transaction. @@ -589,7 +701,7 @@ SD_WRITE8: LD A,H ; End o XOR A ; Success code. SD_WRITE9: PUSH AF - LD A,000H ; Disable SD Card Chip Select to finish. + LD A,0FFH ; Disable SD Card Chip Select to finish. CALL SPICS POP AF RET diff --git a/software/asm/cbios_bank4.asm b/software/asm/cbios_bank4.asm index 65af355..d1eeb24 100644 --- a/software/asm/cbios_bank4.asm +++ b/software/asm/cbios_bank4.asm @@ -1,7 +1,7 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: cbios_bank4.asm -;- Created: October 2018 +;- Created: January 2020 ;- Author(s): Philip Smart ;- Description: Sharp MZ series CPM BIOS System. ;- This assembly language program is written to utilise the banked flashroms added with @@ -11,7 +11,10 @@ ;- Credits: ;- Copyright: (c) 2018-20 Philip Smart ;- -;- History: January 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +;- History: Jan 2020 - Seperated Bank from RFS for dedicated use with CPM CBIOS. +; May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the +; additional and different hardware. The SPI is now onboard the PCB and +; not using the printer interface card. ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify ;- it under the terms of the GNU General Public License as published @@ -38,22 +41,36 @@ ; Common code spanning all banks to ensure that a Monitor is selected upon power up/reset. ;----------------------------------------------------------------------------------------- NOP - XOR A ; We shouldnt arrive here after a reset, ensure MROM and UROM are set to bank 0 - LD (RFSBK1),A ; then a restart will take place as Bank 0 will jump to vector 00000H - LD (RFSBK2),A + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +CBIOS1_0: LD A,(BNKCTRLRST) + DJNZ CBIOS1_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A NOP - ; After switching in Bank 0, it will automatically continue processing in Bank 0 at the XOR A instructionof ROMFS: + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. + ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + ;------------------------------------------------------------------------------- ; Jump table for entry into this pages functions. ;------------------------------------------------------------------------------- - JP ?DSKINIT ; 9 DSKINIT - JP ?SETDRVCFG ; 12 SETDRVCFG - JP ?SETDRVMAP ; 15 SETDRVMAP - JP ?SELDRIVE ; 18 SELDRIVE - JP ?GETMAPDSK ; 21 GETMAPDSK - JP ?DSKREAD ; 24 DSKREAD - JP ?DSKWRITE ; 24 DSKWRITE + ALIGN_NOPS UROMJMPTBL + JP ?DSKINIT ; DSKINIT + JP ?SETDRVCFG ; SETDRVCFG + JP ?SETDRVMAP ; SETDRVMAP + JP ?SELDRIVE ; SELDRIVE + JP ?GETMAPDSK ; GETMAPDSK + JP ?DSKREAD ; DSKREAD + JP ?DSKWRITE ; DSKWRITE ;------------------------------------------------------------------------------- diff --git a/software/asm/include/CPM_Definitions.asm b/software/asm/include/CPM_Definitions.asm index fb4849a..89e90f6 100644 --- a/software/asm/include/CPM_Definitions.asm +++ b/software/asm/include/CPM_Definitions.asm @@ -9,7 +9,10 @@ ;- Credits: ;- Copyright: (c) 2019-20 Philip Smart ;- -;- History: Janaury 2020 - Initial version. +;- History: Jan 2020 - Initial version. +; May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the +; additional and different hardware. The SPI is now onboard the PCB and +; not using the printer interface card. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -26,6 +29,13 @@ ;- along with this program. If not, see . ;-------------------------------------------------------------------------------------------------------- +;----------------------------------------------- +; Features. +;----------------------------------------------- +HW_SPI_ENA EQU 1 ; Set to 1 if hardware SPI is present on the RFS PCB v2 board. +SW_SPI_ENA EQU 0 ; Set to 1 if software SPI is present on the RFS PCB v2 board. +PP_SPI_ENA EQU 0 ; Set to 1 if using the SPI interface via the Parallel Port, ie. for RFS PCB v1 which doesnt have SPI onboard. + ;----------------------------------------------- ; Entry/compilation start points. ;----------------------------------------------- @@ -109,42 +119,43 @@ ENADEBUG EQU 1 ; Enabl ;------------------------------------------------------- ; Function entry points in the CBIOS ROMS ;------------------------------------------------------- +UROMJMPTBL EQU UROMADDR + 00020H ; Position at beginning of each bank of an API jump table of public methods in the bank ; Public functions in CBIOS User ROM Bank 1 - utility functions, ie. Audio. -QREBOOT EQU 9 + UROMADDR -QMELDY EQU 12 + UROMADDR -QTEMP EQU 15 + UROMADDR -QMSTA EQU 18 + UROMADDR -QMSTP EQU 21 + UROMADDR -QBEL EQU 24 + UROMADDR -QMODE EQU 27 + UROMADDR -QTIMESET EQU 30 + UROMADDR -QTIMEREAD EQU 33 + UROMADDR -QCHKKY EQU 36 + UROMADDR -QGETKY EQU 39 + UROMADDR +QREBOOT EQU 0 + UROMJMPTBL +QMELDY EQU 3 + UROMJMPTBL +QTEMP EQU 6 + UROMJMPTBL +QMSTA EQU 9 + UROMJMPTBL +QMSTP EQU 12 + UROMJMPTBL +QBEL EQU 15 + UROMJMPTBL +QMODE EQU 18 + UROMJMPTBL +QTIMESET EQU 21 + UROMJMPTBL +QTIMEREAD EQU 24 + UROMJMPTBL +QCHKKY EQU 27 + UROMJMPTBL +QGETKY EQU 30 + UROMJMPTBL ; Public functions in CBIOS User ROM Bank 2 - Screen / ANSI terminal functions. -QPRNT EQU 9 + UROMADDR -QPRTHX EQU 12 + UROMADDR -QPRTHL EQU 15 + UROMADDR -QANSITERM EQU 18 + UROMADDR +QPRNT EQU 0 + UROMJMPTBL +QPRTHX EQU 3 + UROMJMPTBL +QPRTHL EQU 6 + UROMJMPTBL +QANSITERM EQU 9 + UROMJMPTBL ; Public functions in CBIOS User ROM Bank 3 - SD Card functions. -SD_INIT EQU 9 + UROMADDR -SD_READ EQU 12 + UROMADDR -SD_WRITE EQU 15 + UROMADDR -SD_GETLBA EQU 18 + UROMADDR -SDC_READ EQU 21 + UROMADDR -SDC_WRITE EQU 24 + UROMADDR +SD_INIT EQU 0 + UROMJMPTBL +SD_READ EQU 3 + UROMJMPTBL +SD_WRITE EQU 6 + UROMJMPTBL +SD_GETLBA EQU 9 + UROMJMPTBL +SDC_READ EQU 12 + UROMJMPTBL +SDC_WRITE EQU 15 + UROMJMPTBL ; Public functions in CBIOS User ROM Bank 4 - Floppy Disk Controller functions. -QDSKINIT EQU 9 + UROMADDR -QSETDRVCFG EQU 12 + UROMADDR -QSETDRVMAP EQU 15 + UROMADDR -QSELDRIVE EQU 18 + UROMADDR -QGETMAPDSK EQU 21 + UROMADDR -QDSKREAD EQU 24 + UROMADDR -QDSKWRITE EQU 27 + UROMADDR +QDSKINIT EQU 0 + UROMJMPTBL +QSETDRVCFG EQU 3 + UROMJMPTBL +QSETDRVMAP EQU 6 + UROMJMPTBL +QSELDRIVE EQU 9 + UROMJMPTBL +QGETMAPDSK EQU 12 + UROMJMPTBL +QDSKREAD EQU 15 + UROMJMPTBL +QDSKWRITE EQU 18 + UROMJMPTBL ;----------------------------------------------- @@ -171,10 +182,32 @@ INVDSP: EQU 0E014H NRMDSP: EQU 0E015H SCLDSP: EQU 0E200H SCLBASE: EQU 0E2H -RFSBK1: EQU 0EFFCh ; Select RFS Bank1 (MROM) -RFSBK2: EQU 0EFFDh ; Select RFS Bank2 (User ROM) -RFSRST1: EQU 0EFFEh ; Reset RFS Bank1 to original. -RFSRST2: EQU 0EFFFh ; Reset RFS Bank2 to original. +BNKCTRLRST: EQU 0EFF8H ; Bank control reset, returns all registers to power up default. +BNKCTRLDIS: EQU 0EFF9H ; Disable bank control registers by resetting the coded latch. +HWSPIDATA: EQU 0EFFBH ; Hardware SPI Data register (read/write). +HWSPISTART: EQU 0EFFCH ; Start an SPI transfer. +BNKSELMROM: EQU 0EFFDh ; Select RFS Bank1 (MROM) +BNKSELUSER: EQU 0EFFEh ; Select RFS Bank2 (User ROM) +BNKCTRL: EQU 0EFFFH ; Bank Control register (read/write). + +; +; RFS v2 Control Register constants. +; +BBCLK EQU 1 ; BitBang SPI Clock. +SDCS EQU 2 ; SD Card Chip Select, active low. +BBMOSI EQU 4 ; BitBang MOSI (Master Out Serial In). +CDLTCH1 EQU 8 ; Coded latch up count bit 1 +CDLTCH2 EQU 16 ; Coded latch up count bit 2 +CDLTCH3 EQU 32 ; Coded latch up count bit 3 +BK2A19 EQU 64 ; User ROM Device Select Bit 0 (or Address bit 19). +BK2A20 EQU 128 ; User ROM Device Select Bit 1 (or Address bit 20). + ; BK2A20 : BK2A19 + ; 0 0 = Flash RAM 0 (default). + ; 0 1 = Flash RAM 1. + ; 1 0 = Flasm RAM 2 or Static RAM 0. + ; 1 1 = Reserved. + +BNKCTRLDEF EQU CDLTCH2+CDLTCH1+BBMOSI+SDCS+BBCLK ; Default on startup for the Bank Control register. ;----------------------------------------------- ; IO ports in hardware and values. @@ -212,10 +245,10 @@ SECTORSPERBANK EQU UROMSIZE / ROMSECTORSIZE ; (16) SECTORSPERBLOCK EQU RFSSECTSZ/ROMSECTORSIZE ; (2) ROMSECTORSIZE EQU 128 ROMSECTORS EQU 128 -ROMBK1: EQU 01016H ; CURRENT MROM BANK -ROMBK2: EQU 01017H ; CURRENT USERROM BANK -WRKROMBK1: EQU 01018H ; WORKING MROM BANK -WRKROMBK2: EQU 01019H ; WORKING USERROM BANK +;ROMBK1: EQU 01016H ; CURRENT MROM BANK +;ROMBK2: EQU 01017H ; CURRENT USERROM BANK +;WRKROMBK1: EQU 01018H ; WORKING MROM BANK +;WRKROMBK2: EQU 01019H ; WORKING USERROM BANK ;----------------------------------------------- ; ROM Banks, 0-7 are reserved for alternative @@ -379,7 +412,6 @@ SD_SECPTRK EQU CPM_SD_SEC ; Secto SD_TRACKS EQU CPM_SD_TRK ; Number of virtual tracks per disk image. - ;----------------------------------------------- ; BIOS WORK AREA (MZ80A) ;----------------------------------------------- @@ -443,6 +475,7 @@ TRK0FD2 DS virtual 1 ; FD 2 TRK0FD3 DS virtual 1 ; FD 3 IS AT TRACK 0 = BIT 0 set TRK0FD4 DS virtual 1 ; FD 4 IS AT TRACK 0 = BIT 0 set RETRIES DS virtual 2 ; DATA READ RETRIES +ROMCTL DS virtual 1 ; Rom Paging control register contents. TMPADR DS virtual 2 ; TEMPORARY ADDRESS STORAGE TMPSIZE DS virtual 2 ; TEMPORARY SIZE TMPCNT DS virtual 2 ; TEMPORARY COUNTER diff --git a/software/asm/include/RFS_Definitions.asm b/software/asm/include/RFS_Definitions.asm index 5d86040..f837db8 100644 --- a/software/asm/include/RFS_Definitions.asm +++ b/software/asm/include/RFS_Definitions.asm @@ -9,7 +9,10 @@ ;- Credits: ;- Copyright: (c) 2019-20 Philip Smart ;- -;- History: September 2019 - Initial version. +;- History: Sep 2019 - Initial version. +; May 2020 - Advent of the new RFS PCB v2.0, quite a few changes to accommodate the +; additional and different hardware. The SPI is now onboard the PCB and +; not using the printer interface card. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -26,10 +29,18 @@ ;- along with this program. If not, see . ;-------------------------------------------------------------------------------------------------------- +;----------------------------------------------- +; Features. +;----------------------------------------------- +HW_SPI_ENA EQU 1 ; Set to 1 if hardware SPI is present on the RFS PCB v2 board. +SW_SPI_ENA EQU 0 ; Set to 1 if software SPI is present on the RFS PCB v2 board. +PP_SPI_ENA EQU 0 ; Set to 1 if using the SPI interface via the Parallel Port, ie. for RFS PCB v1 which doesnt have SPI onboard. + ;----------------------------------------------- ; Entry/compilation start points. ;----------------------------------------------- UROMADDR EQU 0E800H ; Start of User ROM Address space. +UROMBSTBL EQU UROMADDR + 020H ; Entry point to the bank switching table. RFSJMPTABLE EQU UROMADDR + 00080H ; Start of jump table. FDCROMADDR EQU 0F000H @@ -105,10 +116,32 @@ INVDSP: EQU 0E014H NRMDSP: EQU 0E015H SCLDSP: EQU 0E200H SCLBASE: EQU 0E2H -RFSBK1: EQU 0EFFCh ; Select RFS Bank1 (MROM) -RFSBK2: EQU 0EFFDh ; Select RFS Bank2 (User ROM) -RFSRST1: EQU 0EFFEh ; Reset RFS Bank1 to original. -RFSRST2: EQU 0EFFFh ; Reset RFS Bank2 to original. +BNKCTRLRST: EQU 0EFF8H ; Bank control reset, returns all registers to power up default. +BNKCTRLDIS: EQU 0EFF9H ; Disable bank control registers by resetting the coded latch. +HWSPIDATA: EQU 0EFFBH ; Hardware SPI Data register (read/write). +HWSPISTART: EQU 0EFFCH ; Start an SPI transfer. +BNKSELMROM: EQU 0EFFDh ; Select RFS Bank1 (MROM) +BNKSELUSER: EQU 0EFFEh ; Select RFS Bank2 (User ROM) +BNKCTRL: EQU 0EFFFH ; Bank Control register (read/write). + +; +; RFS v2 Control Register constants. +; +BBCLK EQU 1 ; BitBang SPI Clock. +SDCS EQU 2 ; SD Card Chip Select, active low. +BBMOSI EQU 4 ; BitBang MOSI (Master Out Serial In). +CDLTCH1 EQU 8 ; Coded latch up count bit 1 +CDLTCH2 EQU 16 ; Coded latch up count bit 2 +CDLTCH3 EQU 32 ; Coded latch up count bit 3 +BK2A19 EQU 64 ; User ROM Device Select Bit 0 (or Address bit 19). +BK2A20 EQU 128 ; User ROM Device Select Bit 1 (or Address bit 20). + ; BK2A20 : BK2A19 + ; 0 0 = Flash RAM 0 (default). + ; 0 1 = Flash RAM 1. + ; 1 0 = Flasm RAM 2 or Static RAM 0. + ; 1 1 = Reserved.` + +BNKCTRLDEF EQU CDLTCH2+CDLTCH1+BBMOSI+SDCS+BBCLK ; Default on startup for the Bank Control register. ;----------------------------------------------- ; IO ports in hardware and values. @@ -143,14 +176,18 @@ RFS_COMNT: EQU 00018h ; COMME TPSTART: EQU 010F0h MEMSTART: EQU 01200h MSTART: EQU 0E900h -DIRMROM: EQU 0006Eh -MFINDMZF: EQU 00071h -MROMLOAD: EQU 00074h MZFHDRSZ EQU 128 RFSSECTSZ EQU 256 MROMSIZE EQU 4096 UROMSIZE EQU 2048 FNSIZE EQU 17 +; +; Monitor ROM Jump Table definitions. +; +MROMJMPTBL: EQU 00070H +DIRMROM: EQU MROMJMPTBL + 00000H +MFINDMZF: EQU MROMJMPTBL + 00003H +MROMLOAD: EQU MROMJMPTBL + 00006H ;----------------------------------------------- ; ROM Banks, 0-7 are reserved for alternative @@ -355,14 +392,15 @@ ROMBK1: EQU 01016H ; CURRE ROMBK2: EQU 01017H ; CURRENT USERROM BANK WRKROMBK1: EQU 01018H ; WORKING MROM BANK WRKROMBK2: EQU 01019H ; WORKING USERROM BANK -SCRNMODE: EQU 0101AH ; Mode of screen, 0 = 40 char, 1 = 80 char. -TMPADR: EQU 0101BH ; TEMPORARY ADDRESS STORAGE -TMPSIZE: EQU 0101DH ; TEMPORARY SIZE -TMPCNT: EQU 0101FH ; TEMPORARY COUNTER -TMPLINECNT: EQU 01021H ; Temporary counter for displayed lines. -TMPSTACKP: EQU 01023H ; Temporary stack pointer save. -SDVER: EQU 01025H -SDCAP: EQU 01026H +ROMCTL: EQU 0101AH ; Current Bank control register setting. +SCRNMODE: EQU 0101BH ; Mode of screen, 0 = 40 char, 1 = 80 char. +TMPADR: EQU 0101CH ; TEMPORARY ADDRESS STORAGE +TMPSIZE: EQU 0101EH ; TEMPORARY SIZE +TMPCNT: EQU 01020H ; TEMPORARY COUNTER +TMPLINECNT: EQU 01022H ; Temporary counter for displayed lines. +TMPSTACKP: EQU 01024H ; Temporary stack pointer save. +SDVER: EQU 01026H +SDCAP: EQU 01027H ; Variables sharing the BUFER buffer, normally the BUFER is only used to get keyboard input and so long as data in BUFER is processed ; before calling the CMT/SD commands and not inbetween there shouldnt be any issue. Also the space used is at the top end of the buffer which is not used so often. ; This frees up memory needed by the CMT and SD card. diff --git a/software/asm/rfs.asm b/software/asm/rfs.asm index eebc642..2e6c1f2 100644 --- a/software/asm/rfs.asm +++ b/software/asm/rfs.asm @@ -1,16 +1,22 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: rfs.asm -;- Created: September 2019 +;- Created: July 2019 ;- Author(s): Philip Smart ;- Description: Sharp MZ series Rom Filing System. ;- This assembly language program is written to utilise the banked flashroms added with ;- the MZ-80A RFS hardware upgrade. ;- ;- Credits: -;- Copyright: (c) 2019 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: September 2018 - Merged 2 utilities to create this compilation. +;- History: July 2019 - Merged 2 utilities to create this compilation. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -43,31 +49,24 @@ ; Common code spanning all banks. ;-------------------------------- ROMFS: NOP - JR ROMFS_0 ; Skip the reset vector. - NOP - NOP - NOP - NOP - NOP - NOP - JP 00000H ; Common point when an alternate bank needs to reset the system. -ROMFS_0: LD A, (ROMBK1) ; Ensure all banks are at default on - CP 4 ; If the ROMBK1 value is 255, an illegal value, then the machine has just started so skip. - JR C, ROMFS_2 - XOR A ; Clear the lower stack space as we use it for variables. - LD B, 7*8 - LD HL, 01000H -ROMFS_1: LD (HL),A - INC HL - DJNZ ROMFS_1 -ROMFS_2: LD (RFSBK1),A ; start up. - LD A, (ROMBK2) - LD (RFSBK2),A - JP MONITOR + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +ROMFS_0: LD A,(BNKCTRLRST) + DJNZ ROMFS_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + LD (ROMCTL),A ; Save to memory the value in the bank control register - this register is used for SPI etc so need to remember its setting. + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. + JP ROMFS_1 ; Skip the reset vector. + JP 00000H ; Other banks will switch at this point thus forcing a full reset. - ; + ALIGN_NOPS UROMBSTBL + + ;------------------------------------------------------------------------------------------ ; Bank switching code, allows a call to code in another bank. ; This code is duplicated in each bank such that a bank switch doesnt affect logic flow. + ;------------------------------------------------------------------------------------------ ; BKSW0to0: PUSH AF LD A, ROMBANK0 ; Calling bank (ie. us). @@ -113,22 +112,50 @@ BKSW0_0: PUSH HL ; Place LD HL, BKSWRET0 ; Place bank switchers return address on stack. EX (SP),HL LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it. - LD (RFSBK2), A ; Bank switch in user rom space, A=bank. + LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value. JP (HL) ; Jump to required function. BKSWRET0: POP AF ; Get bank which called us. - LD (RFSBK2), A ; Return to that bank. + LD (BNKSELUSER), A ; Return to that bank. POP AF RET ; Return to caller. ALIGN RFSJMPTABLE ORG RFSJMPTABLE - ;----------------------------------------- + ;------------------------------------------------------------------------------------------ ; Enhanced function Jump table. - ;----------------------------------------- + ; This table is generally used by the monitor ROM to call functions within the User ROM. + ;------------------------------------------------------------------------------------------ PRTMZF: JP _PRTMZF ;----------------------------------------- + + ;----------------------------------------- + ; Initialisation and startup. + ;----------------------------------------- + ; + ; NB. Bank control registers are left selected. Any software needing access to the top 8 bytes of a + ; ROM/RAM page need to disable them, perform their actions then re-emable. + ; + JP ROMFS_1 ; Skip the reset vector. + ; +ROMFS_1: + LD A, (ROMBK1) ; Ensure all banks are at default + CP 8 ; If the ROMBK1 value is 255, an illegal value, then the machine has just started so initialise memory. + JR C, ROMFS_3 + XOR A ; Clear the lower stack space as we use it for variables. + LD B, 7*8 + LD HL, 01000H +ROMFS_2: LD (HL),A + INC HL + DJNZ ROMFS_2 + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (ROMCTL),A ; Save to memory the value in the bank control register - this register is used for SPI etc so need to remember its setting. + LD A,(ROMBK1) +ROMFS_3: LD (BNKSELMROM),A ; start up. + LD A, (ROMBK2) + LD (BNKSELUSER),A + ;------------------------------------------------------------------------------- ; START OF RFS INITIALISATION AND COMMAND ENTRY PROCESSOR FUNCTIONALITY. ;------------------------------------------------------------------------------- @@ -344,10 +371,11 @@ CMDTABLE: DB 000H | 000H | 000H | 001H ; Bit 2 ; A method used when testing hardware, scope and code will change but one of its purposes is to generate a scope signal pattern. ; -LOCALTEST: LD A,(00000H) - LD (00000H),A +LOCALTEST: LD A,64 + LD (0EFFBH),A JP LOCALTEST + ;------------------------------------------------------------------------------- ; START OF RFS COMMAND FUNCTIONS. ;------------------------------------------------------------------------------- @@ -375,19 +403,19 @@ HEXIYX2: POP AF ; Waste HIROM: LD A, (MEMSW) ; Swap ROM into high range slot. LD A, ROMBANK2 LD (ROMBK1),A ; Save bank being enabled. - LD (RFSBK1),A ; Switch to the hiload rom in bank 2. + LD (BNKSELMROM),A ; Switch to the hiload rom in bank 2. JP 0C000H SETMODE40: LD A, ROMBANK0 ; Switch to 40Char monitor. LD (ROMBK1),A - LD (RFSBK1),A + LD (BNKSELMROM),A LD A, 0 LD (DSPCTL), A JP MONIT SETMODE80: LD A, ROMBANK1 ; Switch to 80char monitor. LD (ROMBK1),A - LD (RFSBK1),A + LD (BNKSELMROM),A LD A, 128 LD (DSPCTL), A JP MONIT @@ -441,7 +469,7 @@ PRTDBG: IF ENADEBUG = 1 PUSH BC PUSH AF LD A,(ROMBK1) - LD (RFSBK1), A ; Set the MROM bank back to original. + LD (BNKSELMROM),A ; Set the MROM bank back to original. CALL PRTHL ; HL LD A, ' ' CALL PRNT @@ -465,7 +493,7 @@ PRTDBG: IF ENADEBUG = 1 LD A, ' ' CALL PRNT LD A,(WRKROMBK1) - LD (RFSBK1), A ; Set the MROM bank back to scanned bank. + LD (BNKSELMROM),A ; Set the MROM bank back to scanned bank. POP AF POP BC POP DE @@ -478,7 +506,7 @@ _PRTMZF: PUSH BC PUSH HL ; LD A,(ROMBK1) ; Ensure main MROM is switched in. - LD (RFSBK1), A + LD (BNKSELMROM),A ; LD A,(SCRNMODE) CP 0 @@ -545,7 +573,7 @@ PRTMZF3: XOR A PRTMZF4: OR A PUSH AF LD A, (WRKROMBK1) - LD (RFSBK1), A + LD (BNKSELMROM),A POP AF POP HL POP DE @@ -553,6 +581,8 @@ PRTMZF4: OR A RET + ; Method to list the directory of the ROM devices. + ; DIRROM: DI ; Disable interrupts as we are switching out the main rom. ; LD A,1 ; Account for the title. @@ -573,7 +603,7 @@ DIRROM: DI ; Disab ; DIRNXTPG: LD A,B LD (WRKROMBK1), A - LD (RFSBK1), A ; Select bank. + LD (BNKSELMROM),A ; Select bank. PUSH BC ; Preserve bank count/block number. PUSH DE ; Preserve file numbering. LD A,C @@ -610,12 +640,12 @@ DIRNXTPG2: LD A,B ; LD A,ROMBANK3 LD (WRKROMBK1),A - LD (RFSBK1), A + LD (BNKSELMROM),A CALL DIRMROM DIRNXTPGX: LD A,(ROMBK1) - LD (RFSBK1), A ; Set the MROM bank back to original. - EI ; No need to block interrupts now as MROM bank restored. - RET ; End of scan, return to monitor + LD (BNKSELMROM),A ; Set the MROM bank back to original. + EI ; No need to block interrupts now as MROM bank restored. + RET ; End of scan, return to monitor ; JP ST1X ; End of scan, return to monitor @@ -644,7 +674,7 @@ FINDMZF0: LD B,MROMPAGES ; First LD D,0 ; File numbering start. FINDMZF1: LD A,B LD (WRKROMBK1), A - LD (RFSBK1), A ; Select bank. + LD (BNKSELMROM),A ; Select bank. FINDMZF2: PUSH BC ; Preserve bank count/block number. PUSH DE ; Preserve file numbering. LD HL,RFS_ATRB ; Add block offset to get the valid block. @@ -663,7 +693,7 @@ FINDMZF2: PUSH BC ; Prese POP DE POP BC LD A,(ROMBK1) - LD (RFSBK1), A ; Set the MROM bank back to original. + LD (BNKSELMROM),A ; Set the MROM bank back to original. JR NZ, FINDMZF4 ; Z set if we found an MZF record. INC HL ; Save address of filename. PUSH HL @@ -684,7 +714,7 @@ FINDMZF3: POP HL LD DE,(TMPADR) ; Original DE put onto stack, original filename into HL LD BC,FNSIZE LD A,(WRKROMBK1) - LD (RFSBK1), A ; Select correct bank for comparison. + LD (BNKSELMROM),A ; Select correct bank for comparison. CALL CMPSTRING POP BC POP DE @@ -702,10 +732,10 @@ FINDMZF5: LD A,B INC B JR FINDMZFNO -FINDMZFYES: ; Flag set by previous test. +FINDMZFYES: ; Flag set by previous test. FINDMZFNO: PUSH AF LD A,(ROMBK1) - LD (RFSBK1), A ; Set the MROM bank back to original. + LD (BNKSELMROM),A ; Set the MROM bank back to original. POP AF POP HL RET @@ -725,19 +755,19 @@ LOADROM1: DI LD A,ROMBANK3 ; Activate the RFS Utilities MROM bank. LD (WRKROMBK1), A - LD (RFSBK1), A + LD (BNKSELMROM),A CALL MFINDMZF ; Try and find the file in User ROM via MROM utility. JR NZ, LROMNTFND ; PUSH BC LD A,(ROMBK1) ; Page in monitor so we can print a message. - LD (RFSBK1), A + LD (BNKSELMROM),A LD DE,MSGLOAD+1 ; Skip initial CR. LD BC,NAME LD HL,PRINTMSG CALL BKSW0to6 LD A,(WRKROMBK1) ; Revert to MROM bank to load the application. - LD (RFSBK1), A + LD (BNKSELMROM),A POP BC ; @@ -746,7 +776,7 @@ LOADROM1: DI LROMNTFND: POP HL ; Dont need execute flag anymore so waste it. LD A,(ROMBK1) - LD (RFSBK1),A + LD (BNKSELMROM),A LD HL,PRINTMSG LD DE,MSGNOTFND ; Not found CALL BKSW0to6 @@ -767,7 +797,7 @@ LROMLOAD: PUSH BC ; LD A,B LD (WRKROMBK1),A - LD (RFSBK1), A + LD (BNKSELMROM),A ; LD DE, IBUFE ; Copy the header into the work area. LD HL, 00000h ; Add block offset to get the valid block. @@ -798,7 +828,7 @@ LROMLOAD: PUSH BC ; C = Block LROMLOAD2: LD A, B LD (WRKROMBK1), A - LD (RFSBK1), A + LD (BNKSELMROM),A LROMLOAD3: PUSH BC LD HL, 00000h @@ -850,7 +880,7 @@ LROMLOAD7: LD A, B LROMLOAD8: POP BC LROMLOAD5: POP HL ; Retrieve execute flag. LD A,(ROMBK1) - LD (RFSBK1), A ; Set the MROM bank back to original. + LD (BNKSELMROM),A ; Set the MROM bank back to original. LD A,L ; Autoexecute turned off? CP 0FFh JP Z,LROMLOAD9 ; Go back to monitor if it has been, else execute. @@ -887,6 +917,7 @@ LROMLOAD9: RET INCLUDE "RFS_Utilities.asm" ; ; Ensure we fill the entire 2K by padding with FF's. + ; ALIGN 0EFFFh DB 0FFh diff --git a/software/asm/rfs_bank1.asm b/software/asm/rfs_bank1.asm index ad3ee0f..b2e293c 100644 --- a/software/asm/rfs_bank1.asm +++ b/software/asm/rfs_bank1.asm @@ -1,16 +1,22 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: rfs_bank1.asm -;- Created: October 2018 +;- Created: July 2019 ;- Author(s): Philip Smart ;- Description: Sharp MZ series Rom Filing System. ;- This assembly language program is written to utilise the banked flashroms added with ;- the MZ-80A RFS hardware upgrade. ;- ;- Credits: -;- Copyright: (c) 2018 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: October 2018 - Merged 2 utilities to create this compilation. +;- History: July 2019 - Merged 2 utilities to create this compilation. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -37,17 +43,30 @@ ;-------------------------------- ; Common code spanning all banks. ;-------------------------------- -ROMFS1: NOP + NOP + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +ROMFS1_0: LD A,(BNKCTRLRST) + DJNZ ROMFS1_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + NOP + NOP + NOP XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 - LD (RFSBK1),A - LD (RFSBK2),A ; and start up - ie. SA1510 Monitor. - ALIGN_NOPS 0E829H - - ; After switching in Bank 0, it will automatically continue processing in Bank 0 at the XOR A instructionof ROMFS: - + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + + ;------------------------------------------------------------------------------------------ ; Bank switching code, allows a call to code in another bank. ; This code is duplicated in each bank such that a bank switch doesnt affect logic flow. + ;------------------------------------------------------------------------------------------ + ALIGN_NOPS UROMBSTBL ; BKSW1to0: PUSH AF LD A, ROMBANK1 ; Calling bank (ie. us). @@ -93,12 +112,12 @@ BKSW1_0: PUSH HL ; P LD HL, BKSWRET1 ; Place bank switchers return address on stack. EX (SP),HL LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it. - LD (RFSBK2), A ; Bank switch in user rom space, A=bank. + LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value. JP (HL) ; Jump to required function. BKSWRET1: POP AF ; Get bank which called us. - LD (RFSBK2), A ; Return to that bank. + LD (BNKSELUSER), A ; Return to that bank. POP AF - RET ; Return to caller. + RET FDCCMD EQU 01000H MOTON EQU 01001H diff --git a/software/asm/rfs_bank2.asm b/software/asm/rfs_bank2.asm index eb0c922..a750532 100644 --- a/software/asm/rfs_bank2.asm +++ b/software/asm/rfs_bank2.asm @@ -1,16 +1,22 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: rfs_bank2.asm -;- Created: October 2018 +;- Created: July 2019 ;- Author(s): Philip Smart ;- Description: Sharp MZ series Rom Filing System. ;- This assembly language program is written to utilise the banked flashroms added with ;- the MZ-80A RFS hardware upgrade. ;- ;- Credits: -;- Copyright: (c) 2018 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: October 2018 - Merged 2 utilities to create this compilation. +;- History: July 2019 - Merged 2 utilities to create this compilation. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -37,14 +43,31 @@ ;-------------------------------- ; Common code spanning all banks. ;-------------------------------- -ROMFS2: NOP - XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 - LD (RFSBK1),A - LD (RFSBK2),A ; and start up - ie. SA1510 Monitor. - ALIGN_NOPS 0E829H + NOP + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +ROMFS2_0: LD A,(BNKCTRLRST) + DJNZ ROMFS2_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + NOP + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. + ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + + ;------------------------------------------------------------------------------------------ ; Bank switching code, allows a call to code in another bank. ; This code is duplicated in each bank such that a bank switch doesnt affect logic flow. + ;------------------------------------------------------------------------------------------ + ALIGN_NOPS UROMBSTBL ; BKSW2to0: PUSH AF LD A, ROMBANK2 ; Calling bank (ie. us). @@ -90,13 +113,12 @@ BKSW2_0: PUSH HL ; P LD HL, BKSWRET2 ; Place bank switchers return address on stack. EX (SP),HL LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it. - LD (RFSBK2), A ; Bank switch in user rom space, A=bank. + LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value. JP (HL) ; Jump to required function. BKSWRET2: POP AF ; Get bank which called us. - LD (RFSBK2), A ; Return to that bank. + LD (BNKSELUSER), A ; Return to that bank. POP AF - RET ; Return to caller. - + RET ;------------------------------------------------------------------------------- ; GENERAL PURPOSE FUNCTIONS. @@ -148,23 +170,64 @@ ADD32: LD BC,(SDSTARTSEC+2) EX DE,HL RET + ; A function from the z88dk stdlib, a delay loop with T state accuracy. + ; + ; enter : hl = tstates >= 141 + ; uses : af, bc, hl +T_DELAY: LD BC,-141 + ADD HL,BC + LD BC,-23 +TDELAYLOOP: ADD HL,BC + JR C, TDELAYLOOP + LD A,L + ADD A,15 + JR NC, TDELAYG0 + CP 8 + JR C, TDELAYG1 + OR 0 +TDELAYG0: INC HL +TDELAYG1: RRA + JR C, TDELAYB0 + NOP +TDELAYB0: RRA + JR NC, TDELAYB1 + OR 0 +TDELAYB1: RRA + RET NC + RET ;------------------------------------------------------------------------------- ; START OF SD CONTROLLER FUNCTIONALITY ;------------------------------------------------------------------------------- - ; Method to initialise the SD card. + ;------------------------------------------------------------------------------- + ; Hardware SPI SD Controller (HW_SPI_ENA = 1) + ; This logic uses the RFS PCB v2+ hardware shift registers to communicate with + ; an SD Card. It is the fastest solution available but has a high IC count. ; -SDINIT: LD A,000H ; CS to high + ; Software SPI SD Controller (SW_SPI_ENA = 1) + ; This logic uses the RFS PCB v2+ logic to simulate the SPI interface with + ; bitbanging techniques. It is similar to the Parallel Port SD Controller + ; but uses logic on the RFS board rather than the parallel port interface. + ; + ; Parallel Port SD Controller (PP_SPI_ENA = 1) + ; This logic uses the standard Sharp MZ-80A Parallel Port for simulating the + ; SPI interface with bitbanging techniques. This interface is then used to + ; communicate with an SD Card. + ;------------------------------------------------------------------------------- + + ; Method to initialise the SD card. Assume that the RFS control registers are enabled, the default state within the RFS environment. + ; +SDINIT: LD A,0FFH ; CS to inactive (high) CALL SPICS ; CALL SPIINIT ; Train SD with our clock. ; - LD A,0FFH ; CS to low + LD A,000H ; CS to active (low) CALL SPICS - LD BC,0FFFFH - + LD BC,01FFFH ; Number of retries before giving up, card not responding. + ; SDINIT1: LD A,CMD0 ; Command 0 LD HL,00000H ; NB. Important, HL should be coded as LH due to little endian and the way it is used in SDCMD. LD DE,00000H ; NB. Important, DE should be coded as ED due to little endian and the way it is used in SDCMD. @@ -274,27 +337,6 @@ SD_EXIT: LD L,A ; Retur LD H,0 RET - ; Method to initialise communications with the SD card. We basically train it to our clock characteristics. - ; This is important, as is maintaining the same clock for read or write otherwise the card may not respond. -SPIINIT: LD B,80 -SPIINIT1: LD A,DOUT_HIGH | CLOCK_HIGH | CS_HIGH ; Output a 1 - OUT (SPI_OUT),A - LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH ; Output a 1 - OUT (SPI_OUT),A - DJNZ SPIINIT1 - RET - - ; Method to set the Chip Select level on the SD card. The Chip Select is active LOW. - ; - ; A = 0 - Set CS HIGH - ; A = 0xFF - Set CS LOW -SPICS: OR A - LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH ; Set CS High if parameter = 0 (ie. disable) - JR Z, SPICS0 - LD A,DOUT_HIGH | CLOCK_LOW | CS_LOW ; Set CS Low if parameter != 0 (ie. disable) -SPICS0: OUT (SPI_OUT),A - RET - ; Method to send a command to the card and receive back a response. ; ; A = CMD to send @@ -346,8 +388,6 @@ SDCMD4: POP HL INC HL POP BC ; Get back number of expected bytes. HL = place in buffer to store response. DJNZ SDCMD3 - LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH - OUT (SPI_OUT),A RET ; Method to send an Application Command to the SD Card. This involves sending CMD55 followed by the required command. @@ -406,72 +446,146 @@ SDACMD3: POP BC ; Succe XOR A RET + ; Method to initialise communications with the SD card. We basically train it to our clock characteristics. + ; This is important, as is maintaining the same clock for read or write otherwise the card may not respond. +SPIINIT: IF HW_SPI_ENA = 1 + ; Hardware SPI on the RFS v2+ PCB. + LD B,10 + LD A, 0FFH ; We need to send 80 '1's, so preload the data register with all 1's, future transmits dont require this as it self loads with 1's. + LD (HWSPIDATA),A +SPIINIT1: LD (HWSPISTART),A ; Commence transmission of an 8bit byte. Runs 1 8MHz, so 1 byte in 1uS, it takes the Z80 2uS for its quickest instruction at 2MHz clock. + DJNZ SPIINIT1 + RET + + ELSE + + ; Software SPI on the RFS v2+ PCB. + IF SW_SPI_ENA = 1 + + ELSE + + ; Software SPI on the centronics parallel port. + LD B,80 +SPIINIT1: LD A,DOUT_HIGH | CLOCK_HIGH | CS_HIGH ; Output a 1 + OUT (SPI_OUT),A + LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH ; Output a 1 + OUT (SPI_OUT),A + DJNZ SPIINIT1 + RET + ENDIF + ENDIF + + ; Method to set the Chip Select level on the SD card. The Chip Select is active LOW. + ; + ; A = 0 - Set CS LOW (active) + ; A = 0xFF - Set CS HIGH (active) +SPICS: IF HW_SPI_ENA = 1 + ; Hardware SPI on the RFS v2+ PCB. + OR A + LD A,(ROMCTL) + SET 1,A ; If we are inactivating CS then set CS high and disable clock by setting BBCLK to low. + RES 0,A + JR NZ, SPICS0 + RES 1,A ; If we are activating CS then set CS low and enable clock by setting BBCLK to high. + SET 0,A +SPICS0: LD (BNKCTRL),A + LD (ROMCTL),A + RET + + ELSE + + ; Software SPI on the RFS v2+ PCB. + IF SW_SPI_ENA = 1 + + ELSE + + ; Software SPI on the centronics parallel port. + OR A + LD A,DOUT_HIGH | CLOCK_LOW | CS_LOW ; Set CS Low if parameter = 0 (ie. enable) + JR Z, SPICS0 + LD A,DOUT_HIGH | CLOCK_LOW | CS_HIGH ; Set CS High if parameter != 0 (ie. disable) +SPICS0: OUT (SPI_OUT),A + RET + ENDIF + ENDIF + ; Method to send a byte to the SD card via the SPI protocol. - ; This method uses the bitbang technique, change if hardware spi is available. + ; This method uses the hardware shift registers. ; ; Input A = Byte to send. ; -SPIOUT: RLCA ; 65432107 - RLCA ; 54321076 - RLCA ; 43210765 - Adjust so that starting bit is same position as Data line. - LD E,A ; E = Character to send. - LD B,8 ; B = Bit count -SPIOUT0: LD A,E - AND DOUT_MASK ; Data bit to data line, clock and cs low. - RLC E -SPIOUT1: OUT (SPI_OUT),A - OR CLOCK_HIGH ; Clock high - OUT (SPI_OUT),A - AND CLOCK_MASK ; Clock low - OUT (SPI_OUT),A - DJNZ SPIOUT0 ; Perform actions for the full 8 bits. - RET +SPIOUT: IF HW_SPI_ENA = 1 + ; Hardware SPI on the RFS v2+ PCB. + LD (HWSPIDATA),A + LD (HWSPISTART),A + RET + + ELSE + + ; Software SPI on the RFS v2+ PCB. + IF SW_SPI_ENA = 1 + + ELSE + + ; Software SPI on the centronics parallel port. + RLCA ; 65432107 + RLCA ; 54321076 + RLCA ; 43210765 - Adjust so that starting bit is same position as Data line. + LD E,A ; E = Character to send. + LD B,8 ; B = Bit count +SPIOUT0: LD A,E + AND DOUT_MASK ; Data bit to data line, clock and cs low. + RLC E +SPIOUT1: OUT (SPI_OUT),A + OR CLOCK_HIGH ; Clock high + OUT (SPI_OUT),A + AND CLOCK_MASK ; Clock low + OUT (SPI_OUT),A + DJNZ SPIOUT0 ; Perform actions for the full 8 bits. + RET + ENDIF + ENDIF ; Method to receive a byte from the SD card via the SPI protocol. - ; This method uses the bitbang technique, change if hardware spi is available. + ; This method uses the hardware shift registers. ; NB. Timing must be very similar in SPIOUT and SPIIN. ; ; Output: A = received byte. ; -SPIIN: LD BC,00800H | SPI_OUT ; B = Bit count, C = clock port - LD L,0 ; L = Character being read. - LD D,DOUT_HIGH | CLOCK_LOW | CS_LOW ; Output a 0 - OUT (C),D ; To start ensure clock is low and CS is low. - LD E,DOUT_HIGH | CLOCK_HIGH | CS_LOW ; Output a 0 -SPIIN1: OUT (C),E ; Clock to high. - IN A,(SPI_IN) ; Input the received bit - OUT (C),D ; Clock to low. - SRL A - RL L - DJNZ SPIIN1 ; Perform actions for the full 8 bits. - LD A,L ; return value - RET +SPIIN: IF HW_SPI_ENA = 1 + ; Hardware SPI on the RFS v2+ PCB. + LD (HWSPISTART),A ; Commence transmission to receive back data from the SD card, we just send 1's. + LD A,(HWSPIDATA) ; Get the data byte. + RET + + ELSE + + ; Software SPI on the RFS v2+ PCB. + IF SW_SPI_ENA = 1 + + ELSE + + ; Software SPI on the centronics parallel port. + LD BC,00800H | SPI_OUT ; B = Bit count, C = clock port + LD L,0 ; L = Character being read. + LD D,DOUT_HIGH | CLOCK_LOW | CS_LOW ; Output a 0 + OUT (C),D ; To start ensure clock is low and CS is low. + LD E,DOUT_HIGH | CLOCK_HIGH | CS_LOW ; Output a 0 +SPIIN1: OUT (C),E ; Clock to high. + IN A,(SPI_IN) ; Input the received bit + OUT (C),D ; Clock to low. + SRL A + RL L + DJNZ SPIIN1 ; Perform actions for the full 8 bits. + LD A,L ; return value + RET + ENDIF + ENDIF + ;------------------------------------------------------------------------------- + ; End of SPI SD Controller + ;------------------------------------------------------------------------------- + - ; A function from the z88dk stdlib, a delay loop with T state accuracy. - ; - ; enter : hl = tstates >= 141 - ; uses : af, bc, hl -T_DELAY: LD BC,-141 - ADD HL,BC - LD BC,-23 -TDELAYLOOP: ADD HL,BC - JR C, TDELAYLOOP - LD A,L - ADD A,15 - JR NC, TDELAYG0 - CP 8 - JR C, TDELAYG1 - OR 0 -TDELAYG0: INC HL -TDELAYG1: RRA - JR C, TDELAYB0 - NOP -TDELAYB0: RRA - JR NC, TDELAYB1 - OR 0 -TDELAYB1: RRA - RET NC - RET ; Method to skip over an SD card input stream to arrive at the required bytes, ; @@ -529,7 +643,7 @@ LBATOADDR: LD HL,(SDSTARTSEC+1) ; SD_READ: PUSH HL ; Store the load address. PUSH BC ; Store the read size. - LD A,0 + LD A,000H CALL SPICS ; Set CS low (active). LD HL,(SDCAP) ; Test to see if CT_BLOCK is available. @@ -596,7 +710,7 @@ SD_READ4: PUSH HL ; Start POP HL LD A,0 ; And exit with success. SD_READ5: PUSH AF - LD A,0 + LD A,0FFH ; De-activate CS. CALL SPICS POP AF RET @@ -615,7 +729,7 @@ SD_READ6: POP BC SD_WRITE: PUSH HL PUSH BC - LD A,0FFH ; Activate CS (set low). + LD A,000H ; Activate CS (set low). CALL SPICS ; Open transaction. @@ -707,7 +821,7 @@ SD_WRITE8: LD A,H ; End o XOR A ; Success code. POP HL ; Get the updated return address to pass back to caller. SD_WRITE9: PUSH AF - LD A,000H ; Disable SD Card Chip Select to finish. + LD A,0FFH ; Disable SD Card Chip Select to finish. CALL SPICS POP AF RET diff --git a/software/asm/rfs_bank3.asm b/software/asm/rfs_bank3.asm index 4de4e82..32abb62 100644 --- a/software/asm/rfs_bank3.asm +++ b/software/asm/rfs_bank3.asm @@ -1,16 +1,22 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: rfs_bank3.asm -;- Created: October 2018 +;- Created: July 2019 ;- Author(s): Philip Smart ;- Description: Sharp MZ series Rom Filing System. ;- This assembly language program is written to utilise the banked flashroms added with ;- the MZ-80A RFS hardware upgrade. ;- ;- Credits: -;- Copyright: (c) 2018 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: October 2018 - Merged 2 utilities to create this compilation. +;- History: July 2019 - Merged 2 utilities to create this compilation. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -42,15 +48,31 @@ MODE80C EQU 0 ;-------------------------------- ; Common code spanning all banks. ;-------------------------------- -ROMFS3: NOP - XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 - LD (RFSBK1),A - LD (RFSBK2),A ; and start up - ie. SA1510 Monitor. - ALIGN_NOPS 0E829H - + NOP + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +ROMFS3_0: LD A,(BNKCTRLRST) + DJNZ ROMFS3_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + NOP + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + + + ;------------------------------------------------------------------------------------------ ; Bank switching code, allows a call to code in another bank. ; This code is duplicated in each bank such that a bank switch doesnt affect logic flow. + ;------------------------------------------------------------------------------------------ + ALIGN_NOPS UROMBSTBL ; BKSW3to0: PUSH AF LD A, ROMBANK3 ; Calling bank (ie. us). @@ -96,14 +118,12 @@ BKSW3_0: PUSH HL ; P LD HL, BKSWRET3 ; Place bank switchers return address on stack. EX (SP),HL LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it. - LD (RFSBK2), A ; Bank switch in user rom space, A=bank. + LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value. JP (HL) ; Jump to required function. BKSWRET3: POP AF ; Get bank which called us. - LD (RFSBK2), A ; Return to that bank. + LD (BNKSELUSER), A ; Return to that bank. POP AF - RET ; Return to caller. - - + RET ;------------------------------------------------------------------------------- ; START OF TAPE/SD CMDLINE TOOLS FUNCTIONALITY diff --git a/software/asm/rfs_bank4.asm b/software/asm/rfs_bank4.asm index 7cd3bb1..f13a121 100644 --- a/software/asm/rfs_bank4.asm +++ b/software/asm/rfs_bank4.asm @@ -1,16 +1,22 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: rfs_bank4.asm -;- Created: October 2018 +;- Created: July 2019 ;- Author(s): Philip Smart ;- Description: Sharp MZ series Rom Filing System. ;- This assembly language program is written to utilise the banked flashroms added with ;- the MZ-80A RFS hardware upgrade. ;- ;- Credits: -;- Copyright: (c) 2018-20 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: October 2018 - Merged 2 utilities to create this compilation. +;- History: July 2019 - Merged 2 utilities to create this compilation. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -38,15 +44,31 @@ ;-------------------------------- ; Common code spanning all banks. ;-------------------------------- -ROMFS4: NOP - XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 - LD (RFSBK1),A - LD (RFSBK2),A ; and start up - ie. SA1510 Monitor. - ALIGN_NOPS 0E829H - + NOP + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +ROMFS4_0: LD A,(BNKCTRLRST) + DJNZ ROMFS4_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + NOP + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + + + ;------------------------------------------------------------------------------------------ ; Bank switching code, allows a call to code in another bank. ; This code is duplicated in each bank such that a bank switch doesnt affect logic flow. + ;------------------------------------------------------------------------------------------ + ALIGN_NOPS UROMBSTBL ; BKSW4to0: PUSH AF LD A, ROMBANK4 ; Calling bank (ie. us). @@ -88,17 +110,16 @@ BKSW4to7: PUSH AF PUSH AF LD A, ROMBANK7 ; Required bank to call. ; -BKSW4_0: PUSH HL ; Place function to call on stack +BKSW4_0: PUSH HL ; Place function to call on stack LD HL, BKSWRET4 ; Place bank switchers return address on stack. EX (SP),HL LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it. - LD (RFSBK2), A ; Bank switch in user rom space, A=bank. + LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value. JP (HL) ; Jump to required function. BKSWRET4: POP AF ; Get bank which called us. - LD (RFSBK2), A ; Return to that bank. + LD (BNKSELUSER), A ; Return to that bank. POP AF - RET ; Return to caller. - + RET ;------------------------------------------------------------------------------- ; START OF CMT CONTROLLER FUNCTIONALITY diff --git a/software/asm/rfs_bank5.asm b/software/asm/rfs_bank5.asm index d886d07..06ac396 100644 --- a/software/asm/rfs_bank5.asm +++ b/software/asm/rfs_bank5.asm @@ -1,16 +1,22 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: rfs_bank5.asm -;- Created: October 2018 +;- Created: July 2019 ;- Author(s): Philip Smart ;- Description: Sharp MZ series Rom Filing System. ;- This assembly language program is written to utilise the banked flashroms added with ;- the MZ-80A RFS hardware upgrade. ;- ;- Credits: -;- Copyright: (c) 2018-20 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: October 2018 - Merged 2 utilities to create this compilation. +;- History: July 2019 - Merged 2 utilities to create this compilation. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -33,20 +39,36 @@ ; USER ROM BANK 5 ; ;====================================== - ORG 0E800h + ORG UROMADDR ;-------------------------------- ; Common code spanning all banks. ;-------------------------------- -ROMFS5: NOP - XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 - LD (RFSBK1),A - LD (RFSBK2),A ; and start up - ie. SA1510 Monitor. - ALIGN_NOPS 0E829H - + NOP + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +ROMFS5_0: LD A,(BNKCTRLRST) + DJNZ ROMFS5_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + NOP + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + + + ;------------------------------------------------------------------------------------------ ; Bank switching code, allows a call to code in another bank. ; This code is duplicated in each bank such that a bank switch doesnt affect logic flow. + ;------------------------------------------------------------------------------------------ + ALIGN_NOPS UROMBSTBL ; BKSW5to0: PUSH AF LD A, ROMBANK5 ; Calling bank (ie. us). @@ -92,14 +114,12 @@ BKSW5_0: PUSH HL ; P LD HL, BKSWRET5 ; Place bank switchers return address on stack. EX (SP),HL LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it. - LD (RFSBK2), A ; Bank switch in user rom space, A=bank. + LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value. JP (HL) ; Jump to required function. BKSWRET5: POP AF ; Get bank which called us. - LD (RFSBK2), A ; Return to that bank. + LD (BNKSELUSER), A ; Return to that bank. POP AF - RET ; Return to caller. - - + RET ALIGN 0EFFFh DB 0FFh diff --git a/software/asm/rfs_bank6.asm b/software/asm/rfs_bank6.asm index 8876ab0..db5b490 100644 --- a/software/asm/rfs_bank6.asm +++ b/software/asm/rfs_bank6.asm @@ -1,16 +1,22 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: rfs_bank6.asm -;- Created: October 2018 +;- Created: July 2019 ;- Author(s): Philip Smart ;- Description: Sharp MZ series Rom Filing System. ;- This assembly language program is written to utilise the banked flashroms added with ;- the MZ-80A RFS hardware upgrade. ;- ;- Credits: -;- Copyright: (c) 2018-20 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: October 2018 - Merged 2 utilities to create this compilation. +;- History: July 2019 - Merged 2 utilities to create this compilation. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -33,20 +39,36 @@ ; USER ROM BANK 6 ; ;====================================== - ORG 0E800h + ORG UROMADDR ;-------------------------------- ; Common code spanning all banks. ;-------------------------------- -ROMFS6: NOP - XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 - LD (RFSBK1),A - LD (RFSBK2),A ; and start up - ie. SA1510 Monitor. - ALIGN_NOPS 0E829H - + NOP + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +ROMFS6_0: LD A,(BNKCTRLRST) + DJNZ ROMFS6_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + NOP + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + + + ;------------------------------------------------------------------------------------------ ; Bank switching code, allows a call to code in another bank. ; This code is duplicated in each bank such that a bank switch doesnt affect logic flow. + ;------------------------------------------------------------------------------------------ + ALIGN_NOPS UROMBSTBL ; BKSW6to0: PUSH AF LD A, ROMBANK6 ; Calling bank (ie. us). @@ -92,14 +114,12 @@ BKSW6_0: PUSH HL ; P LD HL, BKSWRET6 ; Place bank switchers return address on stack. EX (SP),HL LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it. - LD (RFSBK2), A ; Bank switch in user rom space, A=bank. + LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value. JP (HL) ; Jump to required function. BKSWRET6: POP AF ; Get bank which called us. - LD (RFSBK2), A ; Return to that bank. + LD (BNKSELUSER), A ; Return to that bank. POP AF - RET ; Return to caller. - - + RET ;------------------------------------------------------------------------------- ; START OF PRINT ROUTINE METHODS @@ -420,7 +440,7 @@ ATBL: DB 0CCH ; NUL '\0' (null character) ; Message table ; ;-------------------------------------- -MSGSON: DB "+ RFS ", 0ABh, "1.2 **" ,00DH, 000H +MSGSON: DB "+ RFS ", 0ABh, "2.0 **" ,00DH, 000H ; Version 2.0-> as we are now using the v2.x PCB with 4 devices on-board MSGNOTFND: DB "Not Found", 00DH, 000H MSGRDIRLST: DB "ROM Directory:", 00DH, 000H MSGTRM: DB 00DH, 000H @@ -437,7 +457,7 @@ MSGNOTBIN: DB "Not binary", 00DH, 000H MSGLOAD: DB 00DH, "Loading ",'"',0FAH,'"', 00DH, 000H MSGSAVE: DB 00DH, "Filename: ", 000H MSGDIRFULL: DB "Directory full", 00DH, 000H -MSGE1: DB 00DH, "Check sum error!", 00DH, 000H ; Check sum error. +MSGE1: DB 00DH, "Check sum error!", 00DH, 000H ; Check sum error. MSGCMTWRITE:DB 00DH, "Writing ", '"',0FAH,'"', 00DH, 000H MSGOK: DB 00DH, "OK!", 00DH, 000H MSGSAVEOK: DB "Tape image saved.", 00DH, 000H diff --git a/software/asm/rfs_bank7.asm b/software/asm/rfs_bank7.asm index a3f04ce..a69c2eb 100644 --- a/software/asm/rfs_bank7.asm +++ b/software/asm/rfs_bank7.asm @@ -1,16 +1,22 @@ ;-------------------------------------------------------------------------------------------------------- ;- ;- Name: rfs_bank4.asm -;- Created: October 2018 +;- Created: July 2019 ;- Author(s): Philip Smart ;- Description: Sharp MZ series Rom Filing System. ;- This assembly language program is written to utilise the banked flashroms added with ;- the MZ-80A RFS hardware upgrade. ;- ;- Credits: -;- Copyright: (c) 2018-20 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: October 2018 - Merged 2 utilities to create this compilation. +;- History: July 2019 - Merged 2 utilities to create this compilation. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -38,15 +44,31 @@ ;-------------------------------- ; Common code spanning all banks. ;-------------------------------- -ROMFS7: NOP - XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 - LD (RFSBK1),A - LD (RFSBK2),A ; and start up - ie. SA1510 Monitor. - ALIGN_NOPS 0E829H - + NOP + LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +ROMFS7_0: LD A,(BNKCTRLRST) + DJNZ ROMFS7_0 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + NOP + NOP + NOP + XOR A ; We shouldnt arrive here after a reset, if we do, select UROM bank 0 + LD (BNKSELMROM),A + NOP + NOP + NOP + LD (BNKSELUSER),A ; and start up - ie. SA1510 Monitor - this occurs as User Bank 0 is enabled and the jmp to 0 is coded in it. ; + ; No mans land... this should have switched to Bank 0 and at this point there is a jump to 00000H. + JP 00000H ; This is for safety!! + + + ;------------------------------------------------------------------------------------------ ; Bank switching code, allows a call to code in another bank. ; This code is duplicated in each bank such that a bank switch doesnt affect logic flow. + ;------------------------------------------------------------------------------------------ + ALIGN_NOPS UROMBSTBL ; BKSW7to0: PUSH AF LD A, ROMBANK7 ; Calling bank (ie. us). @@ -92,12 +114,12 @@ BKSW7_0: PUSH HL ; P LD HL, BKSWRET7 ; Place bank switchers return address on stack. EX (SP),HL LD (TMPSTACKP),SP ; Save the stack pointer as some old code corrupts it. - LD (RFSBK2), A ; Bank switch in user rom space, A=bank. + LD (BNKSELUSER), A ; Repeat the bank switch B times to enable the bank control register and set its value. JP (HL) ; Jump to required function. BKSWRET7: POP AF ; Get bank which called us. - LD (RFSBK2), A ; Return to that bank. + LD (BNKSELUSER), A ; Return to that bank. POP AF - RET ; Return to caller. + RET ;------------------------------------------------------------------------------- ; START OF MEMORY TEST FUNCTIONALITY diff --git a/software/asm/rfs_mrom.asm b/software/asm/rfs_mrom.asm index f4942b5..748ecf5 100644 --- a/software/asm/rfs_mrom.asm +++ b/software/asm/rfs_mrom.asm @@ -10,9 +10,15 @@ ;- the RFS can read the User Banks and extract required programs. ;- ;- Credits: -;- Copyright: (c) 2018 Philip Smart +;- Copyright: (c) 2018-2020 Philip Smart ;- -;- History: September 2019 - Initial version. +;- History: Sep 2019 - Initial version. +; May 2020 - Bank switch changes with release of v2 pcb with coded latch. The coded +; latch adds additional instruction overhead as the control latches share +; the same address space as the Flash RAMS thus the extra hardware to +; only enable the control registers if a fixed number of reads is made +; into the upper 8 bytes which normally wouldnt occur. Caveat - ensure +; that no loop instruction is ever placed into EFF8H - EFFFH. ;- ;-------------------------------------------------------------------------------------------------------- ;- This source file is free software: you can redistribute it and-or modify @@ -29,101 +35,124 @@ ;- along with this program. If not, see . ;-------------------------------------------------------------------------------------------------------- - ; MONITOR WORK AREA - ; (MZ-80A) + ; MONITOR WORK AREA + ; (MZ-80A) -STACK: EQU 010F0H +STACK: EQU 010F0H - ORG STACK + ORG STACK SPV: IBUFE: ; TAPE BUFFER (128 BYTES) -ATRB: DS virtual 1 ; ATTRIBUTE -NAME: DS virtual FNSIZE ; FILE NAME -SIZE: DS virtual 2 ; BYTESIZE -DTADR: DS virtual 2 ; DATA ADDRESS -EXADR: DS virtual 2 ; EXECUTION ADDRESS -COMNT: DS virtual 92 ; COMMENT -SWPW: DS virtual 10 ; SWEEP WORK -KDATW: DS virtual 2 ; KEY WORK -KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE) -DSPXY: DS virtual 2 ; DISPLAY COORDINATES -MANG: DS virtual 6 ; COLUMN MANAGEMENT -MANGE: DS virtual 1 ; COLUMN MANAGEMENT END -PBIAS: DS virtual 1 ; PAGE BIAS -ROLTOP: DS virtual 1 ; ROLL TOP BIAS -MGPNT: DS virtual 1 ; COLUMN MANAG. POINTER -PAGETP: DS virtual 2 ; PAGE TOP -ROLEND: DS virtual 1 ; ROLL END - DS virtual 14 ; BIAS -FLASH: DS virtual 1 ; FLASHING DATA -SFTLK: DS virtual 1 ; SHIFT LOCK -REVFLG: DS virtual 1 ; REVERSE FLAG -SPAGE: DS virtual 1 ; PAGE CHANGE -FLSDT: DS virtual 1 ; CURSOR DATA -STRGF: DS virtual 1 ; STRING FLAG -DPRNT: DS virtual 1 ; TAB COUNTER -TMCNT: DS virtual 2 ; TAPE MARK COUNTER -SUMDT: DS virtual 2 ; CHECK SUM DATA -CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA -AMPM: DS virtual 1 ; AMPM DATA -TIMFG: DS virtual 1 ; TIME FLAG -SWRK: DS virtual 1 ; KEY SOUND FLAG -TEMPW: DS virtual 1 ; TEMPO WORK -ONTYO: DS virtual 1 ; ONTYO WORK -OCTV: DS virtual 1 ; OCTAVE WORK -RATIO: DS virtual 2 ; ONPU RATIO -BUFER: DS virtual 81 ; GET LINE BUFFER +ATRB: DS virtual 1 ; ATTRIBUTE +NAME: DS virtual FNSIZE ; FILE NAME +SIZE: DS virtual 2 ; BYTESIZE +DTADR: DS virtual 2 ; DATA ADDRESS +EXADR: DS virtual 2 ; EXECUTION ADDRESS +COMNT: DS virtual 92 ; COMMENT +SWPW: DS virtual 10 ; SWEEP WORK +KDATW: DS virtual 2 ; KEY WORK +KANAF: DS virtual 1 ; KANA FLAG (01=GRAPHIC MODE) +DSPXY: DS virtual 2 ; DISPLAY COORDINATES +MANG: DS virtual 6 ; COLUMN MANAGEMENT +MANGE: DS virtual 1 ; COLUMN MANAGEMENT END +PBIAS: DS virtual 1 ; PAGE BIAS +ROLTOP: DS virtual 1 ; ROLL TOP BIAS +MGPNT: DS virtual 1 ; COLUMN MANAG. POINTER +PAGETP: DS virtual 2 ; PAGE TOP +ROLEND: DS virtual 1 ; ROLL END + DS virtual 14 ; BIAS +FLASH: DS virtual 1 ; FLASHING DATA +SFTLK: DS virtual 1 ; SHIFT LOCK +REVFLG: DS virtual 1 ; REVERSE FLAG +SPAGE: DS virtual 1 ; PAGE CHANGE +FLSDT: DS virtual 1 ; CURSOR DATA +STRGF: DS virtual 1 ; STRING FLAG +DPRNT: DS virtual 1 ; TAB COUNTER +TMCNT: DS virtual 2 ; TAPE MARK COUNTER +SUMDT: DS virtual 2 ; CHECK SUM DATA +CSMDT: DS virtual 2 ; FOR COMPARE SUM DATA +AMPM: DS virtual 1 ; AMPM DATA +TIMFG: DS virtual 1 ; TIME FLAG +SWRK: DS virtual 1 ; KEY SOUND FLAG +TEMPW: DS virtual 1 ; TEMPO WORK +ONTYO: DS virtual 1 ; ONTYO WORK +OCTV: DS virtual 1 ; OCTAVE WORK +RATIO: DS virtual 2 ; ONPU RATIO +BUFER: DS virtual 81 ; GET LINE BUFFER ; Starting 1000H - Generally unused bytes not cleared by the monitor. -ROMBK1: EQU 01016H ; CURRENT MROM BANK -ROMBK2: EQU 01017H ; CURRENT USERROM BANK -WRKROMBK1: EQU 01018H ; WORKING MROM BANK -WRKROMBK2: EQU 01019H ; WORKING USERROM BANK -SCRNMODE: EQU 0101AH ; Screen Mode -TMPADR: EQU 0101BH ; TEMPORARY ADDRESS STORAGE -TMPSIZE: EQU 0101DH ; TEMPORARY SIZE -TMPCNT: EQU 0101FH ; TEMPOARY COUNTER -TMPLINECNT:EQU 01021H ; Temporary counter for displayed lines. -TMPSTACKP: EQU 01023H ; Temporary stack pointer save. +ROMBK1: EQU 01016H ; CURRENT MROM BANK +ROMBK2: EQU 01017H ; CURRENT USERROM BANK +WRKROMBK1: EQU 01018H ; WORKING MROM BANK +WRKROMBK2: EQU 01019H ; WORKING USERROM BANK +ROMCTL: EQU 0101AH ; Current Bank control register setting. +SCRNMODE: EQU 0101BH ; Mode of screen, 0 = 40 char, 1 = 80 char. +TMPADR: EQU 0101CH ; TEMPORARY ADDRESS STORAGE +TMPSIZE: EQU 0101EH ; TEMPORARY SIZE +TMPCNT: EQU 01020H ; TEMPORARY COUNTER +TMPLINECNT: EQU 01022H ; Temporary counter for displayed lines. +TMPSTACKP: EQU 01024H ; Temporary stack pointer save. ; EQU TABLE I/O REPORT ;----------------------------------------------- ; Memory mapped ports in hardware. ;----------------------------------------------- -SCRN: EQU 0D000H -ARAM: EQU 0D800H -KEYPA: EQU 0E000h -KEYPB: EQU 0E001h -KEYPC: EQU 0E002h -KEYPF: EQU 0E003h -CSTR: EQU 0E002h -CSTPT: EQU 0E003h -CONT0: EQU 0E004h -CONT1: EQU 0E005h -CONT2: EQU 0E006h -CONTF: EQU 0E007h -SUNDG: EQU 0E008h -TEMP: EQU 0E008h -MEMSW: EQU 0E00CH -MEMSWR: EQU 0E010H -INVDSP: EQU 0E014H -NRMDSP: EQU 0E015H -SCLDSP: EQU 0E200H -RFSBK1: EQU 0EFFCh -RFSBK2: EQU 0EFFDh -RFSRST1: EQU 0EFFEh -RFSRST2: EQU 0EFFFh +SCRN: EQU 0D000H +ARAM: EQU 0D800H +KEYPA: EQU 0E000h +KEYPB: EQU 0E001h +KEYPC: EQU 0E002h +KEYPF: EQU 0E003h +CSTR: EQU 0E002h +CSTPT: EQU 0E003h +CONT0: EQU 0E004h +CONT1: EQU 0E005h +CONT2: EQU 0E006h +CONTF: EQU 0E007h +SUNDG: EQU 0E008h +TEMP: EQU 0E008h +MEMSW: EQU 0E00CH +MEMSWR: EQU 0E010H +INVDSP: EQU 0E014H +NRMDSP: EQU 0E015H +SCLDSP: EQU 0E200H +BNKCTRLRST: EQU 0EFF8H ; Bank control reset, returns all registers to power up default. +BNKCTRLDIS: EQU 0EFF9H ; Disable bank control registers by resetting the coded latch. +HWSPIDATA: EQU 0EFFBH ; Hardware SPI Data register (read/write). +HWSPISTART: EQU 0EFFCH ; Start an SPI transfer. +BNKSELMROM: EQU 0EFFDh ; Select RFS Bank1 (MROM) +BNKSELUSER: EQU 0EFFEh ; Select RFS Bank2 (User ROM) +BNKCTRL: EQU 0EFFFH ; Bank Control register (read/write). + +; +; RFS v2 Control Register constants. +; +BBCLK EQU 1 ; BitBang SPI Clock. +SDCS EQU 2 ; SD Card Chip Select, active low. +BBMOSI EQU 4 ; BitBang MOSI (Master Out Serial In). +CDLTCH1 EQU 8 ; Coded latch up count bit 1 +CDLTCH2 EQU 16 ; Coded latch up count bit 2 +CDLTCH3 EQU 32 ; Coded latch up count bit 3 +BK2A19 EQU 64 ; User ROM Device Select Bit 0 (or Address bit 19). +BK2A20 EQU 128 ; User ROM Device Select Bit 1 (or Address bit 20). + ; BK2A20 : BK2A19 + ; 0 0 = Flash RAM 0 (default). + ; 0 1 = Flash RAM 1. + ; 1 0 = Flasm RAM 2 or Static RAM 0. + ; 1 1 = Reserved.` + +BNKCTRLDEF EQU CDLTCH2+CDLTCH1+BBMOSI+SDCS+BBCLK ; Default on startup for the Bank Control register. ;----------------------------------------------- ; Rom File System Header (MZF) ;----------------------------------------------- -RFS_ATRB: EQU 00000h ; Code Type, 01 = Machine Code. -RFS_NAME: EQU 00001h ; Title/Name (17 bytes). -RFS_SIZE: EQU 00012h ; Size of program. -RFS_DTADR: EQU 00014h ; Load address of program. -RFS_EXADR: EQU 00016h ; Exec address of program. -RFS_COMNT: EQU 00018h ; COMMENT +RFS_ATRB: EQU 00000h ; Code Type, 01 = Machine Code. +RFS_NAME: EQU 00001h ; Title/Name (17 bytes). +RFS_SIZE: EQU 00012h ; Size of program. +RFS_DTADR: EQU 00014h ; Load address of program. +RFS_EXADR: EQU 00016h ; Exec address of program. +RFS_COMNT: EQU 00018h ; COMMENT ;----------------------------------------------- ; ROM Banks, 0-7 are reserved for alternative @@ -150,13 +179,21 @@ ROMBANK10 EQU 10 ; ROMBANK11 EQU 11 ; : CBIOS Bank 4 - Floppy disk controller. - -PRTMZF EQU 0E880H -MZFHDRSZ EQU 128 -RFSSECTSZ EQU 256 -MROMSIZE EQU 4096 -UROMSIZE EQU 2048 -FNSIZE EQU 17 ; Size of tape filename. +; Address definitions. +; +UROMADDR EQU 0E800H ; Start of User ROM Address space. +MROMJMPTBL EQU 00070H ; Fixed location of the Monitor ROM Jump Table. +; +; User ROM Jump Table definitions. +; +RFSJMPTABLE EQU UROMADDR + 00080H ; Entry point to the bank switching table. +PRTMZF EQU RFSJMPTABLE + 00000H ; Entry point into User ROM for the PRTMZF function. +; +MZFHDRSZ EQU 128 +RFSSECTSZ EQU 256 +MROMSIZE EQU 4096 +UROMSIZE EQU 2048 +FNSIZE EQU 17 ; Size of tape filename. ;ROW EQU 25 ;COLW40 EQU 80 @@ -173,40 +210,43 @@ FNSIZE EQU 17 ; Size ORG 00000h MONIT: -MROMBK3: JP START ; The lower part of the rom mimics the SA1510 MROM such that if a reset occurs when - ; this bank is paged in, it starts up and reverts to the SA1510 MROM. +MROMBK3: JP START ; The lower part of the rom mimics the SA1510 MROM such that if a reset occurs when + ; this bank is paged in, it starts up and reverts to the SA1510 MROM. ALIGN_NOPS 0038H - ORG 0038H ; NMI Vector - JP 1038H ; Interrupt routine + ORG 0038H ; NMI Vector + JP 1038H ; Interrupt routine + ALIGN_NOPS 004AH + ORG 004Ah ; As this is not the monitor ROM, if we arrive at START it means a reset without the monitor rom bank being selected ; so we switch it in and do a jump to 0 for reset. - ALIGN_NOPS 004AH - ORG 004Ah START: LD SP, STACK IM 1 CALL ?MODE LD B,0FFH LD HL,NAME CALL ?CLER + ; + CALL INITBNKCTL NOP NOP NOP - NOP - NOP - NOP - LD A,(ROMBK2) ; User ROM to default. - LD (RFSBK2), A - LD A, (ROMBK1) ; Monitor ROM to default. - LD (RFSBK1), A + ; + LD A,(ROMBK2) ; User ROM to default. + LD (BNKSELUSER), A + LD A, (ROMBK1) ; Monitor ROM to default. + LD (BNKSELMROM), A ; Location for STRT1 in monitor ROM (just after Colour RAM clear call). After the bank switch we should - ; resume at this point in original monitor. - ORG 06Ch + ; resume at this point in original monitor - ie. line commencing LD HL,TIMIN @ 006CH. + ORG 0006Ch JR START + ALIGN_NOPS MROMJMPTBL + ORG MROMJMPTBL + ;----------------------------------------- ; Enhanced function Jump table. ;----------------------------------------- @@ -221,36 +261,68 @@ MROMLOAD: JP _MROMLOAD ; ;==================================== + ; Method to initialise the bank control registers to a default state. + ; +INITBNKCTL:LD B,16 ; If we read the bank control reset register 15 times then this will enable bank control and then the 16th read will reset all bank control registers to default. +INITBNK_1: LD A,(BNKCTRLRST) + DJNZ INITBNK_1 ; Apply the default number of coded latch reads to enable the bank control registers. + LD A,BNKCTRLDEF ; Set coded latch, SDCS high, BBMOSI to high and BBCLK to high which enables SDCLK. + LD (BNKCTRL),A + LD (ROMCTL),A ; Save to memory the value in the bank control register - this register is used for SPI etc so need to remember its setting. + RET + + + ; Function to select a User Bank. If Carry is clear upon entry, on exit the control registers will be disabled. If carry is set then the control registers are left active. + ; +SELUSRBNK: PUSH BC + PUSH AF + LD A,(ROMCTL) ; Get current setting for the coded latch, ie. number of reads needed to enable it. + RRA + RRA + CPL + AND 00FH ; Preserve bits 3-1, bit 0 is always 0 on the 74HCT191 latch. + LD B,A ; Set value to B for loop. + LD A,(BNKCTRLDIS) +SELUSRBNK1:LD A,(BNKSELUSER) + DJNZ SELUSRBNK1 + POP AF + POP BC + LD (BNKSELUSER),A ; Select the required bank. + JR C,SELUSRBNK2 ; If Carry is set by caller then leave the control registers active. + LD (BNKCTRLDIS),A ; Disable the control registers, value of A is not important. +SELUSRBNK2:RET + + ; HL contains address of block to check. ISMZF: PUSH BC PUSH DE PUSH HL ; LD A,(HL) - CP 001h ; Only interested in machine code images. + CP 001h ; Only interested in machine code images. JR NZ, ISMZFNOT ; INC HL - LD DE,NAME ; Checks to confirm this is an MZF header. - LD B,FNSIZE ; Maximum of 17 characters, including terminator in filename. + LD DE,NAME ; Checks to confirm this is an MZF header. + LD B,FNSIZE ; Maximum of 17 characters, including terminator in filename. ISMZFNXT: LD A,(HL) LD (DE),A - CP 00Dh ; If we find a terminator then this indicates potentially a valid name. + CP 00Dh ; If we find a terminator then this indicates potentially a valid name. JR Z, ISMZFVFY - CP 020h ; >= Space + CP 020h ; >= Space JR C, ISMZFNOT - CP 05Dh ; =< ] + CP 05Dh ; =< ] JR C, ISMZFNXT3 ISMZFNXT2: CP 091h - JR C, ISMZFNOT ; DEL or > 0x7F, cant be a valid filename so this is not an MZF header. + JR C, ISMZFNOT ; DEL or > 0x7F, cant be a valid filename so this is not an MZF header. ISMZFNXT3: INC DE INC HL DJNZ ISMZFNXT - JR ISMZFNOT ; No end of string terminator, this cant be a valid filename. + JR ISMZFNOT ; No end of string terminator, this cant be a valid filename. ISMZFVFY: LD A,B CP FNSIZE - JR Z,ISMZFNOT ; If the filename has no length it cant be valid, so loop. -ISMZFYES: CP A ; Set zero flag to indicate match. + JR Z,ISMZFNOT ; If the filename has no length it cant be valid, so loop. +ISMZFYES: CP A ; Set zero flag to indicate match. ISMZFNOT: POP HL POP DE POP BC @@ -266,13 +338,14 @@ _DIRMROM: PUSH BC ; C = Block in page ; D = File sequence number. ; - LD B,USRROMPAGES ; First 16x2K pages are reserved in User bank. - LD C,0 ; Block in page. + LD B,USRROMPAGES ; First 16x2K pages are reserved in User bank. + LD C,0 ; Block in page. DIRNXTPG: LD A,B LD (WRKROMBK2), A - LD (RFSBK2), A ; Select bank. - PUSH BC ; Preserve bank count/block number. - PUSH DE ; Preserve file numbering. + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK + PUSH BC ; Preserve bank count/block number. + PUSH DE ; Preserve file numbering. LD A,C IF RFSSECTSZ >= 512 RLCA @@ -282,7 +355,7 @@ DIRNXTPG: LD A,B ENDIF LD B,A LD C,0 - LD HL,0E800h + RFS_ATRB ; Add block offset to get the valid block address. + LD HL,0E800h + RFS_ATRB ; Add block offset to get the valid block address. ADD HL,BC CALL ISMZF POP DE @@ -290,18 +363,19 @@ DIRNXTPG: LD A,B JR NZ, DIRNOTMZF ; CALL _PRTMZF - INC D ; Next file sequence number. + INC D ; Next file sequence number. DIRNOTMZF: INC C LD A,C - CP UROMSIZE/RFSSECTSZ ; Max blocks per page reached? + CP UROMSIZE/RFSSECTSZ ; Max blocks per page reached? JR C, DIRNXTPG2 LD C,0 INC B DIRNXTPG2: LD A,B - CP 000h ; User rom has 256 banks of 2K, so stop when we wrap round to 0. + CP 000h ; User rom has 256 banks of 2K, so stop when we wrap round to 0. JR NZ, DIRNXTPG LD A,(ROMBK2) - LD (RFSBK2), A ; Set the User bank back to original. + SCF ; Select the required user bank and Set carry so that the control registers remain enabled. + CALL SELUSRBNK POP DE POP BC RET @@ -309,10 +383,12 @@ DIRNXTPG2: LD A,B ; Wrapper to call the User ROM function to display the MZF filename. _PRTMZF: LD A,(ROMBK2) - LD (RFSBK2), A + SCF ; Select the required user bank and Set carry so that the control registers remain enabled. + CALL SELUSRBNK CALL PRTMZF LD A,(WRKROMBK2) - LD (RFSBK2), A + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK RET @@ -324,13 +400,13 @@ _PRTMZF: LD A,(ROMBK2) ; D = File sequence number. ; Z set if found. _MFINDMZF: PUSH DE - LD (TMPADR), HL ; Save name of program to load. - EX DE, HL ; String needed in DE for conversion. - LD HL,0FFFFh ; Tag the filenumber as invalid. + LD (TMPADR), HL ; Save name of program to load. + EX DE, HL ; String needed in DE for conversion. + LD HL,0FFFFh ; Tag the filenumber as invalid. LD (TMPCNT), HL - CALL ConvertStringToNumber ; See if a file number was given instead of a filename. - JR NZ, FINDMZF0 ; - LD (TMPCNT), HL ; Store filenumber making load by filenumber valid. + CALL ConvertStringToNumber ; See if a file number was given instead of a filename. + JR NZ, FINDMZF0 ; + LD (TMPCNT), HL ; Store filenumber making load by filenumber valid. ; ; Scan MROM Bank @@ -338,16 +414,17 @@ _MFINDMZF: PUSH DE ; C = Block in page ; D = File sequence number. ; -FINDMZF0: POP DE ; Get file sequence number in D. - LD B,USRROMPAGES ; First 8 pages are reserved in User ROM bank. - LD C,0 ; Block in page. - ;LD D,0 ; File numbering start. +FINDMZF0: POP DE ; Get file sequence number in D. + LD B,USRROMPAGES ; First 8 pages are reserved in User ROM bank. + LD C,0 ; Block in page. + ;LD D,0 ; File numbering start. FINDMZF1: LD A,B LD (WRKROMBK2), A - LD (RFSBK2), A ; Select bank. -FINDMZF2: PUSH BC ; Preserve bank count/block number. - PUSH DE ; Preserve file numbering. - LD HL,0E800h + RFS_ATRB ; Add block offset to get the valid block. + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK +FINDMZF2: PUSH BC ; Preserve bank count/block number. + PUSH DE ; Preserve file numbering. + LD HL,0E800h + RFS_ATRB ; Add block offset to get the valid block. LD A,C IF RFSSECTSZ >= 512 RLCA @@ -362,45 +439,46 @@ FINDMZF2: PUSH BC ; Preserve bank count/block numb CALL ISMZF POP DE POP BC - JR NZ, FINDMZF4 ; Z set if we found an MZF record. - INC HL ; Save address of filename. + JR NZ, FINDMZF4 ; Z set if we found an MZF record. + INC HL ; Save address of filename. PUSH HL LD HL,(TMPCNT) LD A,H - CP 0FFh ; If TMPCNT tagged as 0xFF then we dont have a filenumber so must match filename. + CP 0FFh ; If TMPCNT tagged as 0xFF then we dont have a filenumber so must match filename. JR Z, FINDMZF3 - LD A,L ; Check file number, load if match + LD A,L ; Check file number, load if match CP D - JR NZ, FINDMZF3 ; Check name just in case. + JR NZ, FINDMZF3 ; Check name just in case. POP HL - JR FINDMZFYES ; Else the filenumber matches so load the file. + JR FINDMZFYES ; Else the filenumber matches so load the file. FINDMZF3: POP HL PUSH DE PUSH BC - LD DE,(TMPADR) ; Original DE put onto stack, original filename into DE + LD DE,(TMPADR) ; Original DE put onto stack, original filename into DE LD BC,FNSIZE CALL CMPSTRING POP BC POP DE JR Z, FINDMZFYES - INC D ; Next file sequence number. + INC D ; Next file sequence number. FINDMZF4: INC C LD A,C - CP UROMSIZE/RFSSECTSZ ; Max blocks per page reached? + CP UROMSIZE/RFSSECTSZ ; Max blocks per page reached? JR C, FINDMZF5 LD C,0 INC B FINDMZF5: LD A,B - CP 000h ; User ROM has 256 banks of 2K, so stop when we wrap around to zero. + CP 000h ; User ROM has 256 banks of 2K, so stop when we wrap around to zero. JR NZ, FINDMZF1 INC B JR FINDMZFNO -FINDMZFYES: ; Flag set by previous test. +FINDMZFYES: ; Flag set by previous test. FINDMZFNO: PUSH AF LD A,(ROMBK2) - LD (RFSBK2), A ; Set the MROM bank back to original. + SCF ; Select the required user bank and Set carry so that the control registers remain enabled. + CALL SELUSRBNK POP AF RET @@ -414,10 +492,11 @@ FINDMZFNO: PUSH AF _MROMLOAD: PUSH BC LD A,B LD (WRKROMBK2),A - LD (RFSBK2), A + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK ; - LD DE, IBUFE ; Copy the header into the work area. - LD HL, 0E800h ; Add block offset to get the valid block. + LD DE, IBUFE ; Copy the header into the work area. + LD HL, 0E800h ; Add block offset to get the valid block. LD A,C IF RFSSECTSZ >= 512 RLCA @@ -445,7 +524,8 @@ _MROMLOAD: PUSH BC ; C = Block LROMLOAD2: LD A, B LD (WRKROMBK2), A - LD (RFSBK2), A + OR A ; Select the required user bank and Clear carry so that the control registers are disabled. + CALL SELUSRBNK LROMLOAD3: PUSH BC LD HL, 0E800h @@ -468,23 +548,23 @@ LROMLOAD3: PUSH BC JR NC, LROMLOAD4 LD BC, (TMPSIZE) LD HL, 0 -LROMLOAD4: LD (TMPSIZE), HL ; HL contains remaining amount of bytes to load. +LROMLOAD4: LD (TMPSIZE), HL ; HL contains remaining amount of bytes to load. POP HL ; - LD A, B ; Pre check to ensure BC is not zero. + LD A, B ; Pre check to ensure BC is not zero. OR C JR Z, LROMLOAD8 LDIR LD BC, (TMPSIZE) - LD A, B ; Post check to ensure we still have bytes + LD A, B ; Post check to ensure we still have bytes OR C JR Z, LROMLOAD8 ; - LD (TMPADR),DE ; Address we are loading into. + LD (TMPADR),DE ; Address we are loading into. POP BC LROMLOAD6: INC C LD A, C - CP UROMSIZE/RFSSECTSZ ; Max blocks per page reached? + CP UROMSIZE/RFSSECTSZ ; Max blocks per page reached? JR C, LROMLOAD7 LD C, 0 INC B @@ -498,7 +578,8 @@ LROMLOAD7: LD A, B LROMLOAD8: POP BC LROMLOAD5: PUSH AF LD A,(ROMBK2) - LD (RFSBK2), A ; Set the MROM bank back to original. + SCF ; Select the required user bank and Set carry so that the control registers remain enabled. + CALL SELUSRBNK POP AF RET diff --git a/software/hdr/cpm22.HDR b/software/hdr/cpm22.HDR index ac24447..251dcf6 100644 Binary files a/software/hdr/cpm22.HDR and b/software/hdr/cpm22.HDR differ diff --git a/software/roms/MROM_256.bin b/software/roms/MROM_256.bin index 17491b7..b7ccdfa 100644 Binary files a/software/roms/MROM_256.bin and b/software/roms/MROM_256.bin differ diff --git a/software/roms/USER_ROM_256.bin b/software/roms/USER_ROM_256.bin index d1f99b4..a1add12 100644 Binary files a/software/roms/USER_ROM_256.bin and b/software/roms/USER_ROM_256.bin differ diff --git a/software/roms/cbios.rom b/software/roms/cbios.rom index 885ea1e..a8b0153 100644 Binary files a/software/roms/cbios.rom and b/software/roms/cbios.rom differ diff --git a/software/roms/cbios_bank1.rom b/software/roms/cbios_bank1.rom index c1185c8..36910b8 100644 Binary files a/software/roms/cbios_bank1.rom and b/software/roms/cbios_bank1.rom differ diff --git a/software/roms/cbios_bank2.rom b/software/roms/cbios_bank2.rom index 82b7ca7..b3033ef 100644 Binary files a/software/roms/cbios_bank2.rom and b/software/roms/cbios_bank2.rom differ diff --git a/software/roms/cbios_bank3.rom b/software/roms/cbios_bank3.rom index 8df8913..66b7312 100644 Binary files a/software/roms/cbios_bank3.rom and b/software/roms/cbios_bank3.rom differ diff --git a/software/roms/cbios_bank4.rom b/software/roms/cbios_bank4.rom index 82d9b74..975e888 100644 Binary files a/software/roms/cbios_bank4.rom and b/software/roms/cbios_bank4.rom differ diff --git a/software/roms/rfs.rom b/software/roms/rfs.rom index 3e35b79..ead2c34 100644 Binary files a/software/roms/rfs.rom and b/software/roms/rfs.rom differ diff --git a/software/roms/rfs_mrom.rom b/software/roms/rfs_mrom.rom index 27f12b8..b3263d4 100644 Binary files a/software/roms/rfs_mrom.rom and b/software/roms/rfs_mrom.rom differ